Abstract

Flash memory is import and has been popularly used in our daily life. Two type of flash memory devices are proposed to circumvent the scaling down limitation of the conventional planar technology and to improve the operation performance. One is based on the used of stack tunnel dielectric and the other on the used of vertical double-gate structure.
In this study, we design two groups of tunnel dielectric for flash memory devices. The first group is to used a single Si3N4 or Si3N4/SiO¬2 stack tunnel dielectric, followed by rapid-thermal-annealing (RTA); the second group is to used a single HfOxNy or HfOxNy/SiO2 stack tunnel dielectric, followed by post-deposition annealing (PDA). It is experimentally observed that flash memory devices with a stack tunnel dielectric have better operation performance than those with a single layer. In the first sample group, devices with a stack tunnel dielectric composed of a thick Si3N4 layer and a thin SiO2 layer exhibits better operating performance. For the RTA samples, flash memory devices subjected at 800oC temperature of their tunnel dielectrics exhibit better performance. In the second sample group, those with a stack tunnel dielectric composed of a thick HfOxNy layer and a thin SiO2 layer exhibits the best operation performance. For the PDA samples, the flash memory devices with an HfOxNy/SiO2 stack tunnel dielectric subjected to a PDA temperature at 850oC exhibit the best operation performance.
Various structures and operation characterization of the vertical double gate flash memory devices are studied by the device simulator MEDICI, to circumvent the scaling down limitation of the conventional planar technology. Novel vertical double gate flash memory devices with SiGe/Si heterojunction by band-gap engineering exhibits better operation performance. The Ge content in the SiGe junction of vertical double gate flash memory devices with SiGe/Si heterojunction improves operation performances.

摘要

　　快閃記憶體已愈來愈重要並廣泛地應用於日常生活中。為改善快閃記憶體之操作特性，及解決元件微縮過程中所面臨之問題，本文提出利用堆疊結構穿隧介電層之快閃記憶體，並另設計新型垂直結構搭配矽化鍺材料之快閃記憶體。
本文設計兩類之快閃記憶體穿隧介電層: 第一類為利用單層Si3N4或不同組成比之Si3N4/ SiO2堆疊結構，再配合不同溫度之快速熱處理；第二類為利用單層HfOXNY或不同組成比之 HfOXNY/ SiO2堆疊結構，再配合不同溫度之快速熱處理。 由實驗知，堆疊結構較單層穿隧介電層之操作特性佳。於第一類元件：堆疊結構之穿隧介電層中，厚的Si3N4搭配薄的SiO2堆疊結構之穿隧介電層，擁有較佳之元件操作特性；不同溫度之快速熱處理中，800 oC快速熱處理之穿隧介電層，擁有較佳之元件操作特性。於第二類元件：堆疊結構之穿隧介電層中，厚的HfOXNY搭配薄的SiO2堆疊結構之穿隧介電層，擁有最佳之元件操作特性；不同溫度之快速熱處理中，850 oC快速熱處理之穿隧介電層，擁有最佳之元件操作特性。
避免元件微縮過程中所面臨之問題，本文應用元件模擬軟體MEDICI 設計不同垂直結構並配合不同操作條件之快閃記憶體。搭配矽/矽化鍺異質接於面垂直結構雙閘極快閃記憶體，擁有較佳之元件操作特性。隨著增加矽化鍺之鍺含量於搭配矽/矽化鍺異質接面之垂直結構雙閘極快閃記憶體，快閃記憶體之操作特性跟著改善。

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