可變區塊大小的移動估計是 H.264具有高效率影像壓縮的因素之一，此移動估計由兩部分組成：整數移動估計和分數移動估計。整數移動估計搜尋整個搜尋視窗並找出每個區塊的整數移動向量，分數移動估計並進一步優化此移動向量至四分之一像素精準度。根據我們的實驗結果發現，可變區塊大小的移動估計佔整個H.264影像壓縮時間的百分之九十以上，因此，在高解析度的影像應用中，可變區塊大小移動估計的硬體加速器是必要的。
在此論文的第一部份中，我們針對整數移動估計提出了一個高記憶體效率以及高運算平行度的硬體架構，此架構具有十六個二維陣列，每個二維陣列由16x16個運算單元組成，每四個二維陣列為一組且平行處理一個現行區塊和四個參考區塊的比對，四組陣列平行處理四個現行區塊的比對。此外，我們利用多個參考區塊的高度重疊性，提出了一個資料重複使用的方法來降低所需的記憶體讀取數量，和現行的層級C資料重複使用方法比較，我們提出的方法可以節省百分之九十八的記憶體讀取和百分之七十五的記憶體容量。合成結果顯示，此架構在130MHz的頻率下，可以及時處理高解析度(1920x1088)的影像。我們並且提出了一個公式來比較不同硬體架構的設計效率，結果顯示我們架構的設計效率比現行最好的架構還要高出百分之七十二。
在此論文的第二部份中，我們提出了一個高效能分數移動估計的硬體架構，此架構具有三個平行運算的引擎，一個處理4x4和8x8 的區塊，一個處理4x8和8x4的區塊，第三個處理16x16 、16x8 和8x16的區塊。此外，針對絕對誤差和的運算，我們提出了一個資源共用的方法並節省百分之三十三的所需硬體。合成結果顯示，此架構在154MHz的頻率下，可以及時處理高解析度(1920x1088)的影像，並且比現行最好的架構更有效率。

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