隨著製程進入到奈米層級，封裝和晶片在實體設計和生產製造過程中皆面臨許多的挑戰。近年來，隨著電路設計的複雜度不斷提升，封裝的針腳數快速成長導致封裝針腳配置和印刷電路板脫離繞線變得極為困難。然而大部分前作都把針腳配置和脫離繞線視為兩個獨立的問題而缺乏一個共同設計的總體觀點。除了封裝之外，晶片製造也面臨一個新的挑戰。單次曝光浸潤式微影技術在22奈米及以下製程時印刷晶片佈局會出現困難。雙重曝光微影技術已經成為在22奈米及以下製程時印刷佈局圖案的一個有前途的解決方案。我們很希望在精細繞線階段時就考慮雙重曝光微影技術，因為這樣可以用最少線跡數輕鬆地去分解一個佈局。

在本論文中，我們提出三個最佳化的技術去解決實體設計的問題。這些問題包括印刷電路板脫離繞線和在晶片層級考慮雙重曝光技術的精細繞線。首先我們提出一個方法去同時解決限制針腳配置和脫離繞線，這個方法是針對一個現場可編程邏輯閘陣列的封裝放在一個採用穿透導孔的印刷電路板上。其次我們針對在一個封裝放在一個採用盲導孔的印刷電路板上的針腳配置和脫離繞線的問題。我們提出一個對針腳配置和盲導孔使用作共同設計最佳化的演算法，以及一個在考慮盲導孔技術下同時作多層脫離繞線的演算法。最後我們提出一個考慮雙重曝光的精細繞線演算法以達成光罩使用量的平衡。大量的實驗結果顯示我們提出的最佳化技術在印刷電路板脫離繞線和考慮雙重曝光的晶片繞線下是有效和有效率的。

As the technology node scales down to nanometer range, packages and chips both face many challenges in physical design and manufacturing process. With the increasing complexity of circuit design in recent years, package pin assignment and printed circuit board (PCB) escape routing have become extremely difficult due to the fast increasing pin count of a package. However, most previous works often treat the pin assignment and the escape routing as two independent problems without a global view of co-design.
Besides packages, a new challenge arises in the manufacturing process of a chip. Single-exposure immersion lithography has difficulty in printing the layout pattern under 22nm technology node and beyond. Double patterning lithography (DPL) has emerged as a promising solution to print layout pattern for sub-22nm technology nodes. It is desired to consider DPL during the detailed routing stage so that the layout can be decomposed effortlessly with the minimum number of stitches.

In this dissertation, we propose three optimization techniques to solve the physical design problems including the PCB escape routing and chip-level double patterning-aware detailed routing. First, we propose a simultaneous approach that can solve the constrained pin assignment and escape routing for an FPGA package on a through-via-based PCB. Second, we address the pin assignment and escape routing for a package on a blind-via-based PCB. We propose a pin assignment and blind-via usage co-optimization algorithm and a simultaneous multi-layer escape routing algorithm based on the blind-via technology. Finally, we propose a double patterning-aware detailed routing algorithm to balance the mask usage.
Extensive experimental results show that our proposed optimization techniques are effective and efficient for PCB escape routing and double patterning-aware chip routing.

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