三維堆疊近來已成為一個積體電路相當流行的技術，而其中基於矽中介層的三維堆疊電路是在業界的主要趨勢，尤其是應用在處理器與記憶體的堆疊。去評估且找出基於矽中介層的三維堆疊最具經濟效益的測試流程是很重要的。我們提出了一個基於矽中介層的三維堆疊電路的成本模型，並且包括了晶片到晶圓 (D2W) 和晶片到晶片 (D2D) 兩種堆疊方式，成本裡也包含了製造成本和測試成本。我們將成本模型實作成成本分析工具，且使用此工具尋找最具經濟效益的測試流程。從結果我們可以發現，在某些應用中，測試流程若有包含反覆的堆疊測試 (iterative KGS test) 和矽中介層堆疊前測試 (pre-bond interposer test)，當堆疊良率低於99.2%和矽中介層良率低於99%時可以顯著地減少成本。另外也描繪了一個Shmoo圖表示在不同產品良率以及堆疊晶片顆數下所需封裝測試良率的底限。而三種不同的三維記憶體修復方案的成本也做了比較，結果表示當備用晶片數目大於二十顆時，使用區塊層級備分記憶體 (macro level redundancy) 可以得到最低的成本。對於不同的應用，該模型可找出測試動作執行的標準以及計算出成本值，這也可以幫助工程師去找出最具經濟效益的測試流程與系統架構。

Three-dimensional (3D) integration has recently become a popular technology for integrated circuits (IC). 3D IC with the passive silicon interposer is currently the main trend in the industry, especially for processor-memory integration. Evaluating the economic efficiency of test operations in the interposer-based 3D IC thus is important. We propose a cost model for interposer-based 3D IC with 3D memory repair schemes, including the Die-to-Wafer (D2W) and Die-to-Die (D2D) stacking. The cost model contains the manufacturing cost and test cost. A tool which is based on the proposed cost model is developed. We use this tool for cost analysis and for finding the most cost effective test flow. The results show that, in some applications, test flows including the iterative known-good stack (KGS) test and the pre-bond interposer test significantly reduce the cost, when the KGS test yield is lower than 99.2% and the pre-bond interposer test yield is lower than 99%. The Shmoo plot is depicted to show the lower bound of the yield of the final package level test, given the number of stacked dies and the final yield. The total costs of three types of 3D memory repair schemes are compared. The result shows that, among three different 3D memory repair schemes, the macro level redundancy with over 20 redundancy dies has the lowest cost. For different applications, the proposed model evaluates the execution criterion or cost values, which helps the designers to determine the most cost effective test flow and the system architecture.

[1] W. A. Wulf, S. A. McKee, “Hitting the MemoryWall: Implications of the
Obvious,” Computer Architecture News, 23(1):20–24, March 1995.
[2] K. Banerjee et al, “3-D ICs: A Novel Chip Design for Improving
Deep-Submicrometer Interconnect Performance and Systems-on-Chip
Integration,” Proceedings of the IEEE, 89(5):602–633, May 2001.
[3] B. Swinnen et al, “3D Integration by Cu-Cu Thermo-Compression Bonding of
Extremely Thinned Bulk-Si Die Containing 10μm Pitch Through-Si Vias,”
Proceedings IEEE International Electron Devices Meeting (IEDM), pages 1–4,
May 2006.
[4] R. S. Patti, “Three-Dimensional Integrated Circuits and the Future of
System-on-Chip Designs,” Proceedings of the IEEE, 94(6):1214–1224, June
2006.
[5] E. Beyne, B. Swinnen, “3D System Integration Technologies,“ Proceedings of
IEEE International Conference on Integrated Circuit Design and Technology
(ICICDT), pages 1–3, June 2007.
[6] P. Garrou, C. Bower, P. Ramm, editors. Handbook of 3D Integration –
Technology and Applications of 3D Integrated Circuits. Wiley-VCH, Weinheim,
Germany, August 2008.
[7] J. V. Olmen et al, “3D Stacked IC Demonstration using a Through Silicon Via
First Approach,” Proceedings IEEE International Electron Devices Meeting
(IEDM), pages 1–4, December 2008.
[8] J.-Q. Lu, "3-D Hyperintegration and Packaging Technologies for Micronano
Systems," Proceedings of the IEEE, vol. 97, no. I, pp. 18-30, Jan. 2009.
[9] H. H. Jones, Technical Viability of Stacked Silicon Interconnect Technology.
Xilinx, October 2010. White Paper, see
http://www.xilinx.com/publications/technology/stacked-siliconinterconnect-tech
nology-ibs-research.pdf.
[10] P. Dorsey, Xilinx Stacked Silicon Interconnect Technology Delivers
Breakthrough FPGA Capacity, Bandwidth, and Power Efficiency. Xilinx,
October 2010. White Paper, see http://www.xilinx.com/support/documentat
[11] B. Banijamali, S. Ramalingam, K. Nagarajan, R.Chaware, "Advanced Reliability
Study of TSV Interposers and Interconnects for the 28nm Technology FPGA,"
Electronic Components and Technology Conference (ECTC), pp.285-290, May
31 2011-June 3 2011.
[12] Y. Chen, D. Niu, Y. Xie, and K. Chakrabarty, “Cost-Effective Integration of
Three-Dimensional (3D) ICs Emphasizing Testing Cost Analysis,”
Computer-Aided Design (ICCAD), IEEE/ACM International Conference on, Nov.
2010, pp. 471 –476.
[13] X. Dong, Y. Xie, “System-Level Cost Analysis and Design Exploration for
Three-Dimensional Integrated Circuits (3D ICs),” Design Automation
Conference (ASP-DAC), Asia and South Pacific, Jan. 2009, pp. 234 –241.
[14] M. Taouil, S. Hamdioui, K. Beenakker, E. Marinissen, “Test Cost Analysis for
3D Die-to-Wafer Stacking,” Asian Test Symposium (ATS), Dec. 2010, pp. 435 –
441.
[15] D. Velenis, M. Stucchi, E. Marinissen, B. Swinnen, E. Beyne, “Impact of 3D
Design Choices on Manufacturing Cost,” 3D System Integration Conference
(3DIC), IEEE International Conference on, Sept. 2009, pp. 1 –5.
[16] D. Velenis, E. Marinissen, and E. Beyne, “Cost Effectiveness of 3D Integration
Options,” 3D Systems Integration Conference (3DIC), IEEE International
Conference on, Nov. 2010, pp. 1 –6.
[17] E. J. Marinissen, Y. Zorian, "Testing 3D Chips Containing Through-Silicon
Vias," Test Conference (ITC), pp.1-11, 1-6 Nov. 2009
[18] C.-W. Chou, J.-F. Li, J.-J. Chen, D.-M. Kwai, Y.-F. Chou, C.-W. Wu, "A Test
Integration Methodology for 3D Integrated Circuits," Test Symposium (ATS),
pp.377-382, 1-4 Dec. 2010
[19] C.-W. Wu, S.-K. Lu, J-F. Li , "On Test and Repair of 3D Random Access
Memory," Design Automation Conference (ASP-DAC), 17th Asia and South
Pacific, pp.744-749, Jan. 30 2012-Feb. 2 2012
[20] W. R. Davis, J. Wilson, S. Mick, J. Xu, H. Hua, C. Mineo, A. M. Sule, M. Steer,
P.D. Franzon, "Demystifying 3D ICs: The Pros and Cons of Going Vertical,"
Design & Test of Computers, IEEE , vol.22, no.6, pp. 498- 510, Nov.-Dec. 2005
[21] Y.-T. Hsing, L.-M. Denq, C,-H. Chen, C.-W. Wu, "Economic Analysis of the
HOY Wireless Test Methodology," Design & Test of Computers, IEEE , vol.27,
no.3, pp.20-30, May-June 2010
[22] P. Nag, A. Gattiker, S. Wei, R. Blanton, W. Maly, “Modeling the Economics of
Testing: a DFT Perspective,” Design Test of Computers, IEEE, vol. 19, no. 1, pp.
29 –41,Jan/Feb 2002.
[23] M. Lee, L.-M. Denq, C-W. Wu, "A Memory Built-In Self-Repair Scheme Based
on Configurable Spares," Computer-Aided Design of Integrated Circuits and
Systems, IEEE Transactions on, vol.30, no.6, pp.919-929, June 2011
[24] C.-T. Huang, C.-F. Wu, J.-F. Li, C.-W. Wu, “Built-In Redundancy Analysis for
Memory Yield Improvement,” IEEE Trans. Reliab., vol. 52, no. 4, pp. 386–399,
Dec. 2003.
[25] C.-W. Wu, S.-K. Lu, Jin-Fu Li, "On Test and Repair of 3D Random Access
Memory," Design Automation Conference (ASP-DAC), 17th Asia and South
Pacific , pp.744-749, Jan. 30 2012-Feb. 2 2012
[26] Y.-F. Chou; D.-M. Kwai; C.-W. Wu, "Memory Repair by Die Stacking with
Through Silicon Vias," Memory Technology, Design, and Testing (MTDT), IEEE
International Workshop on, pp.53-58, Aug. 31 2009-Sept. 2 2009
[27] K. Smith, P. Hanaway, M. Jolley, R. Gleason, E. Strid, T. Daenen, L. Dupas, B.
Knuts, E. J. Marinissen, M. Van Dievel, “Evaluation of TSV and Micro-Bump
Probing for Wide I/O Testing,” Test Conference (ITC), IEEE International, Sept.
2011, pp. 1 –10.
[28] E. J. Marinissen, J. Verbree, M. Konijnenburg, “A Structured and Scalable Test
Access Architecture for TSV-Based 3D Stacked ICs,” in VLSI Test Symposium
(VTS), 28th, April 2010, pp. 269 –274.
[29] C.-C. Chi, E.J. Marinissen, S.K. Goel, C.-W. Wu, "Post-Bond Testing of
2.5D-Sics and 3D-Sics Containing a Passive Silicon Interposer Base," Test
Conference (ITC), 2011 IEEE International , vol., no., pp.1-10, 20-22 Sept. 2011
[30] C.-C. Chi, E.J. Marinissen, S.K. Goel, C.-W. Wu, "Multi-visit TAMs to Reduce
the Post-Bond Test Length of 2.5D-SICs with a Passive Silicon Interposer Base,"
Asian Test Symposium (ATS), pp.451-456, 20-23 Nov. 2011
[31] J.-Q. Lu, "3-D Hyperintegration and Packaging Technologies for Micro-Nano
Systems," Proceedings of the IEEE , vol.97, no.1, pp.18-30, Jan. 2009
[32] C.-Y. Lo, Y.-T. Hsing, L.-M. Denq, C.-W. Wu, "SOC Test Architecture and
Method for 3-D ICs," Computer-Aided Design of Integrated Circuits and
Systems, IEEE Transactions on , vol.29, no.10, pp.1645-1649, Oct. 2010
[33] Y.-J. Huang, J.-F. Li, J.-J. Chen, D.-M. Kwai, Y.-F. Chou, C.-W. Wu, "A
Built-In Self-Test Scheme for the Post-Bond Test of TSVs In 3D ICs," VLSI Test
Symposium (VTS), pp.20-25, 1-5 May 2011
[34] P.-Y. Chen, C.-W. Wu, D.-M. Kwai, "On-Chip TSV Testing for 3D IC before
Bonding Using Sense Amplification," Asian Test Symposium (ATS), pp.450-455,
23-26 Nov. 2009
[35] P.-Y. Chen, C.-W. Wu, D.-M. Kwai, "On-Chip Testing of Blind and
Open-Sleeve TSVs for 3D IC Before Bonding," VLSI Test Symposium (VTS),
pp.263-268, 19-22 April 2010
[36] C.-C. Chi, E.J. Marinissen, S.K. Goel, C.-W. Wu, "DFT Architecture for
3D-SICs with Multiple Towers," European Test Symposium (ETS), pp.51-56,
23-27 May 2011
[37] T. Williams, N. Brown, “Defect Level as a Function of Fault Coverage,”
Computers, IEEE Transactions on, vol. C-30, no. 12, pp. 987 –988, Dec. 1981.
[38] L.-M. Denq, C.-W. Wu, "A Hybrid BIST Scheme for Multiple Heterogeneous
Embedded Memories," Asian Test Symposium (ATS), pp.349-354, 8-11 Oct.
2007