無線通訊技術正在改變人類的生活型態，在未來可移動式全球互通微波存取系統，因為其寬頻且可攜式的特性，幾乎可取代今日ADSL加Wi-Fi的網路接取模式。尤其在無線傳輸下，通道編碼為一必要之過程。在的規格書IEEE 802.16e版本中，低密度奇偶檢查碼(Low Density Parity Check Codes, 以下簡稱LDPC碼)即為其中的規範之一種類。由於低密度奇偶檢查碼有很好的抗衰落性，編碼增益很高，接收機在較低的信噪比情況下仍然可以擁有較低的誤碼率，可以使覆蓋範圍得到提升。
由於低密度奇偶檢查碼有很好的錯誤更正效能，改良後的解碼方式有低複雜度特性，而且可具有高的吞吐量(throughput)，因此許多下一代的通道編碼技術紛紛採用低密度奇偶檢查碼，如無線網路(IEEE 802.11n)、無線都會區域網路(IEEE 802.16e)、銅線百億位元乙太網路標準(IEEE 802.2an)與數位視訊廣播衛星標準(DVB-S2)。低密度奇偶檢查碼的錯誤更正效能與疊代(iteration)次數成正比，所以在雜訊較高的通道傳輸時，就需要較多的疊代次數，因此疊代次數就成為低密度奇偶檢查碼效能的關鍵。

在本論文中，我們提出了一個具有高吞吐量的低密度奇偶檢查碼解碼架構，此設計可適用於可移動式全球互通微波存取系統上。以縱向混合解碼演算法進行解碼運算為基礎，採用了一個重新安排的解碼流程來加快解碼收斂的速度。由元件可程式邏輯閘陣列進行了實體的驗證，並經由90奈米的製程技術，實現了晶片佈局。在固定 6次遞迴解碼的情況下，可以達到最高的傳輸速率為每秒746百萬位元，其功率消耗為90mW。

In this thesis, we propose a high-throughput low-density
parity-check (LDPC) decoder architecture, which is compatible with
mobile WiMAX system. Based on vertical shuffled scheduling, we
proposed a scheduling method to arrange decoding sequence. The
architecture is verified by FPGA system board. Moreover, 90nm
technology is used to implement the physical layout. Under 6
decoding iterations, the decoder can achieve highest 746Mb/s, and
the power consumption is 90mW.

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