在本篇論文中，我們將以動態位元線暫存資料(Dynamic Bitline Latch, DBL)的觀念為基礎，提出三種應用於分裂式NOR型(DIvide NOR, DINOR)快閃式記憶體陣列，多重頁平行(Multiple Page Parallel, MPP)寫入的操作方法，分別為(1)簡單式動態位元線暫存資料(Simple DBL)、(2)無重新寫入之動態位元線暫存資料(DBL without Refresh)及(3)重新寫入之動態位元線暫存資料(DBL with Refresh)，並對所提出的三種操作模式做比較。整體而言，在此類型的操作方法中，由於輸入的資料均暫時被儲存於次位元線(Sub-Bitline)的電容中，位於同一條主位元線(Main-Wordline)上所有被選到的記憶體均可在同一時間完成寫入的動作，而在有寫入的資料被限制住的情況之下，臨界電壓的變化也會因此而變小，因此該方法具有寫入速度高及臨界電壓變化小的優點。在另一方面，我們可以藉由在控制閘極加偵測用的脈衝，使得記憶體在不同臨界電壓值導通，藉以控制收斂的臨界電壓值。由我們的實驗結果可得知，本論文中所提出的三種操作模式均有良好的操作特性及可靠度。除此之外，在本論文中還將對操作波形的設計做個別的討論，並提出建議的操作條件。為了得到較好的操作特性，高閘極偶合比例(Gate Coupling Ratio)及高位元線電容比例(Bitline Capacitor Ratio) 是必須的，對於32K大小的位元數而言，所需的操作時間小於0.18ms。總而言之，多重頁平行寫入的操作方法適合高速、小臨界電壓變化及高可靠度的應用。

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