隨著網路應用與資訊產業的蓬勃發展，各種社交網絡資料的傳輸頻寬需求增加，人們對於數據傳輸速度及傳輸量的需求呈現爆炸性成長，因此超高速與低成本的相關元件及系統急遽增加。而傳輸速度為4×25Gb/s的系統，此規格已成為現今市面可見的產品。此傳輸線的接頭包含光電轉換元件及電路，與傳輸電訊號之系統進行光電轉換，再利用低損耗高頻寬且低干擾的光纖(fiber)取代傳統的電纜進行多通道訊號傳輸。
第二章中，我們將建立一組25Gb/s光通訊前端模組進行模擬，正確建立光電元件如PD(Photo detector)、LD(Laser Diode)及封裝寄生效應的模型，並設計訊號傳輸線在高傳輸速率時的訊號品質，並連接商用規格的放大器，進行前端系統模組模擬。
第三章中，我們將PD(Photo detector)、LD(Laser Diode)與本實驗室所設計的轉阻放大器(TIA)及雷射驅動器(Laser Diode Driver)進行整合，以打線方式將元件與電路連接，並進行光電系統性量測，在量測部份，電訊號可達到40Gb/s的傳輸速度，在接收端光電轉換部份可達到20Gb/s的傳輸速度。在雷射驅動器的部份，設計圖騰柱輸出級放大器將雙端輸入轉成單端輸出驅動雷射二極體，在電訊號部份可達32Gb/s的傳輸速度，發射端光電轉換部份可達12.5Gb/s。
第四章中，我們應用另一種光通訊發射端架構，採用光調變器(Modulator)與驅動電路(Modulator Driver)，光調變器需要相當大的電壓擺幅才能將電訊號轉變至光訊號，一般來說至少需要4-5V的電壓擺幅，因此在電路設計上將是很大的挑戰，我們採用分散式放大器架構並使用迴授式架構保護電晶體免於崩壞，在量測結果，傳輸速度可達40Gb/s，並且有4V的擺幅。
第五章中，我們將介紹未來方向，未來網路需求持續增加，行動通訊網路、電信網路、資料中心網路及光纖到家等，因此400Gb/s速率的系統架構已開始在全球最大的光通訊研討會OFC所探討。

With the explosive development of web applications and information industry, the increasing demands of transmission bandwidth for the various social networks, and the explosive of data transmission and processing, the demand of transmission speed in communication systems has grown rapidly recently. One recent specification targets the transmission speed up to 4×25Gb/s. The optical communication front end module includes optoelectronics deivces, ampilfier and connector, so that the signal can be transmitted by light.
In chapter 2, we build the equivalent circuit models of optoelectronics device such as photo detector and laser diode. Modeling of of these components are of extreme importance for high frequency applications. We perform system level simulation for the front end module in ADS.
In chapter 3, we focus on the integration and characterization of the photo detectors (PDs) with transimpedance amplifiers with two different topologies. The first one adopts a modified regulated cascode (RGC) as input stage and the technique of reversed triple resonance network (RTRN) for bandwidth enhancement thus it can operate at low supply voltage. The second design uses a common-gate configuration as input stage and the technique of RTRN. The measured electrical eye diagrams can be up to 40Gb/s and the optical eye diagram can be up to 20Gb/s. We also integrate and characterize a laser diode driver with the laser diode. The driver adpots totem pole output stage and asymmetric inductors. The totem pole configuration can easily transfer the differential singal to single ended. With the proposed asymmetric inductors, both singal paths will have a similar gain leading to a good characteristic of eye diagram. The electrical eye diagram can up to 32Gb/s. The driver wirebond with the driver and the measured optical to electrical eye diagram can be up to 12.5 Gb/s.
In chapter 4, we propose two topologies of differential modulator drivers for silicon modulator. The first one adopts cascode stage distributed amplifier which have large bandwidth and high output voltage swing. The second adopts resister feedback cascode stage distributed amplifier to prevent transistors from breakdown. The modulator driver reachs 4V with an operation speed of 40Gb/s.
In chapter 5, the conclusions are given with the recommendation of future works.

[1] TE connectivity technical report, “End-to-End Communications with advanced fiber optic technologies”, http://www.te.com/.
[2] TE connectivity technical report, “QSFP28 TRANSCEIVER”, http://www.te.com/.
[3] T. Ma, Y. Jiang, Y. Fan, X. Lin, Z. Zhu, “A design of transition between microstrip line and semiconductor devices with gold-bonding wire,” IEEE Symp. Microwave, Antenna, Propagation, and EMC Technologies for Wireless Communication (MAPE), pp.303-305, Nov. 2011
[4] T. Shih, P. Tseng, Y. Lai, W. Cheng, “A 25 Gbit/s transmitter optical sub-assembly package employing cost-effective TO-CAN material and process,” IEEE J. Lightwave Technology, vol. 30, no. 6, pp.834,840, March 15, 2012
[5] S. Kang, J. Lee, J. Huh, K. Kim, J. Lee, “A compact ROSA module for serial 40-Gb/s optical transceiver,” IEEE Electric Components and Technology Conference (ECTC), pp.1850-1854, May 2013
[6] “High Speed Analog Design and Application Seminar,” Texas Instrument.
[7] J. Gao, X. Li, J. Flucke, G. Boeck, “Direct parameter-extraction method for laser diode rate-equation model,” IEEE J. Lightwave Technology, vol.22, no. 6, pp.1604,1609, June 2004
[8] T. Shih, P. Tseng, Y. Lai, W. Cheng, “Compact TO-CAN header with bandwidth excess 40 GHz,” IEEE J. Lightwave Technology, vol.29, no.17, pp.2538,2544, Sept.1, 2011
[9] Shih-Hao Huang, Wei-Zen Chen, Yu-Wei Chang and Yang-Tung Huang, “A 10-Gb/s OEIC with meshed spatially-modulated photo detector in 0.18-μm CMOS technology,” IEEE J. Solid-State Circuits, vol. 46, no. 5, pp.1158-1169, May 2011.
[10] Wei-Zen Chen and Da-Shin Lin, “A 90-dB 10-Gb/s optical receiver analog front-end in a 0.18-um CMOS technology,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst, vol. 15, no. 3, pp. 358–365, Mar. 2007.
[11] Wei-Zen Chen, Ying-Lien Cheng and Da-Shin Lin, “ A 1.8v 10-gb/s fully integrated cmos optical receiver analog front-end,” IEEE J. Solid-State Circuits, vol. 40, no. 6, pp. 1388-1396, Jun. 2005.
[12] Chao-Yung Wang, Chao-Shiun Wang, and Chorng-Kuang Wang, "An 18-mW two-stage CMOS transimpedance amplifier for 10 Gb/s optical application." Solid-State Circuits Conference (A-SSCC), 2007.
[13] Chih-Fan Liao and Shen-Iuan Liu, “40 Gb/s transimpedance-AGC amplifier and CDR circuit for broadband data receivers in 90 nm CMOS,” IEEE J.Solid-State Circuits, vol. 43, no. 3, pp. 642–655, Mar. 2008.
[14] Samira Bashiri, Calvin Plett, Jorge Aguirre and Peter Schvan,“A 40gb/s transimpedance amplifier in 65nm CMOS technology,” in Proc. IEEE Int. Symp. on Circuits and Systems, 2010, pp. 757 –760.
[15] Joohwa Kim and Buckwalter, J.F, “A 40-Gb/s optical transceiver front-end in 45 nm SOI CMOS,” IEEE Journal of Solid-State Circuits, vol. 47, no. 3, pp. 1-4, March 2012.
[16] J. Kim and James F. Buckwalter, “Bandwidth enhancement with low groupdelay variation for a 40-Gb/s transimpedance amplifier,” IEEE Trans.Circuits Syst. I: Reg. Papers, vol. 57, no. 8, pp. 1964–1972, Aug. 2010.
[17] Chih-Chun Tang, Chia-Hsin Wu, and Shen-Iuan Liu, "Miniature 3-D inductors in standard CMOS process," IEEE Journal of Solid-State Circuits, vol 37, no.4, pp.471-480, Apr.2002.
[18] H. Shigematsu, M. Sato, I. Hirose, F. Brewer and M. Rodwell, "40Gb/s CMOS distributed amplifier for fiber-optic communication systems," Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International, 2004, pp. 476-540 Vol.1.
[19] Ming-Da Tsai, Huei Wang, Jui-Feng Kuan and Chih-Sheng Chang, "A 70GHz cascaded multi-stage distributed amplifier in 90nm CMOS technology," ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005., San Francisco, CA, 2005, pp. 402-606 Vol. 1.
[20] J. C. Chien and L. H. Lu, "A 40-Gb/s high-gain distributed amplifiers with cascaded gain stages in 0.18-μm CMOS," in IEEE Journal of Solid-State Circuits, vol. 42, no. 12, pp. 2715-2725, Dec. 2007.
[21] C. Yuen, K. Laursen, Duc Chu and K. Mar, "50 GHz high output voltage distributed amplifiers for 40 Gb/s EO modulator driver application," Microwave Symposium Digest, 2002 IEEE MTT-S International, Seattle, WA, USA, 2002, pp. 481-484 vol.1.
[22] C. Lee, L. c. Cho and S. i. Liu, "A 0.1-25.5-GHz Differential Cascaded-Distributed Amplifier in 0.18- μm CMOS Technology," 2005 IEEE Asian Solid-State Circuits Conference, Hsinchu, 2005, pp. 129-132.
[23] Tai-Yuan Chen, Jun-Chau Chien and Liang-Hung Lu, "A 45.6-GHz matrix distributed amplifier in 0.18-nm CMOS," Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005., 2005, pp. 119-122.
[24] H. Shigematsu, M. Sato, T. Hirose and Y. Watanabe, "A 54-GHz distributed amplifier with 6-VPP output for a 40-Gb/s LiNbO3 modulator driver," in IEEE Journal of Solid-State Circuits, vol. 37, no. 9, pp. 1100-1105, Sep 2002.
[25] C. Y. Hsiao, T. Y. Su and S. S. H. Hsu, "CMOS Distributed Amplifiers Using Gate–Drain Transformer Feedback Technique," in IEEE Transactions on Microwave Theory and Techniques, vol. 61, no. 8, pp. 2901-2910, Aug. 2013.
[26] Liang-Hung Lu, Tai-Yuan Chen and Yi-Jay Lin, "A 32-GHz non-uniform distributed amplifier in 0.18-μm CMOS," in IEEE Microwave and Wireless Components Letters, vol. 15, no. 11, pp. 745-747, Nov. 2005.
[27] S. J. Mahon, "A Novel Non-Uniform Distributed Amplifier/Attenuator for Millimetre-wave Transmitter MMICs," 2006 IEEE MTT-S International Microwave Symposium Digest, San Francisco, CA, 2006, pp. 814-817.
[28] J. Kim, Buckwalter, J.F. , "A 40-Gb/s Optical Transceiver Front-End in 45 nm SOI CMOS," IEEE J. of Solid-State Circuits, vol.47, no.3, pp.615–626, March 2012.
[29] S. Nakano, M. Nogawa, H. Nosaka, A. Tsuchiya, H. Onodera and S. Kimura, "A 25-Gb/s 480-mW CMOS modulator driver using area-efficient 3D inductor peaking," Solid-State Circuits Conference (A-SSCC), 2015 IEEE Asian, Xiamen, 2015
[30] M. S. Kao, F. T. Chen, Y. H. Hsu and J. M. Wu, "20-Gb/s CMOS EA/MZ Modulator Driver With Intrinsic Parasitic Feedback Network," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 22, no. 3, pp. 475-483, March 2014.
[31] 陳聖文, “應用於光連結系統之高速前端電路與光電介面交換機設計,”國立清華大學電子工程研究所碩士論文,2012。
[32] 邱柏崴, “光連結系統之高速收發機電路與交換機設計及量測,”國立清華大學電子工程研究所碩士論文,2013。
[33] 劉彥廷, “超高速光通訊前端電路設計,” 國立清華大學電子工程研究所碩士論文,2014。
[34] 廖景輝, “高速光通訊前端類比電路設計” 國立清華大學電子工程研究所碩士論文,2015。
[35] 王柏鈞, “高速光通訊傳輸端電路設計” 國立清華大學電子工程研究所碩士論文,2015。