隨著超大型積體電路製程技術愈來愈進步，當電晶體製程尺寸進入奈米等級之後，製程變異(process variations)的影響已經變成是造成晶片良率下降的主要原因之一，近年來，補償製程變異的後矽電路調整技術已經廣泛的被研究，例如用全電路電壓調整(full-chip tuning)，但該技術將會在沒有受到製程變異的電路部分增加額外的動態功率或靜態功率消耗。所以我們之前提出以列電壓為基礎的調控電路結構(row-based tunable architecture)，此結構是可逐列調整以列為單位的電路操作電壓(supply voltage)，藉由測試診斷技術和以滿足性為基礎(SAT-based)的調整電壓設定演算法來做增加電路的操作速度或降低電路的功率消耗來做最佳化的電路電壓調整。不過上述方法相關的測試診斷技術需要耗費相當大量的測試成本，而測試成本來自於多重測試時脈方法量測電路所需要的延遲路徑。

在本篇論文中，我們提出的方法將使用固定少量的測試時脈建立測試資料，而我們就可以使用事先建立的測試資料來分類晶片測試結果且把該晶片分類到不同的電壓設定，這樣就可節省多重測試時脈測試的測試成本。在實驗結果顯示我們所提出來的方法，相較於藉由測試診斷技術和以滿足性為基礎的調整電壓設定演算法的方法平均約只要花費4%的測試成本，另外調整過電路操作電壓設定的晶片樣本可修復良率達到86%到118%。

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