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研究生： 游傑安
You, Jie-An
論文名稱： 以記憶體儲存之突觸可塑性電路實現
The Implementation of Synaptic Plasticity Circuit by Memory
指導教授： 陳新
Chen, hsin
口試委員: 彭盛裕
Peng, Sheng-Yu
金雅琴
King, Ya-Chin
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電子工程研究所
Institute of Electronics Engineering
論文出版年： 2019
畢業學年度： 108
語文別： 英文
論文頁數： 65
中文關鍵詞： 電阻式記憶體 、仿生神經突觸 、類神經網路
外文關鍵詞： Resistive random access memory, Artificial Synapse, Neural network
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    • 　人工智慧是時下最熱門的話題之一，不論是汽車、醫療、或是金融等產業，都能夠跟AI一詞有所聯繫。而其中的類神經網路，便是將電腦系統以仿人類大腦的方式進行運算。相比傳統的電腦，人腦擁有強大的學習及推理判斷的能力，不論是圖像或是語音的認知能力都是電腦遠比不上的。因此，研究低功耗、並能平行且大量運算的類神經網路，便是值得深入的主題。
    　　在類神經網路中，神經元間的突觸連結強度被認為與記憶和學習有極大的關係。本論文主要是在研究透過運用記憶體電路的方式，實現類神經網路中的突觸，以調變突觸連結強度及儲存調變的結果。論文共分為前後兩大部分。前半部分是在量測及探討特殊元件，接觸點電阻式記憶體是否適合當作類比式仿突觸記憶體。但後來因量測結果不慎理想，並且其調變電路在28nm製程的下線因設計規範驗證(DRC)問題而不被接受，故轉為使用靜態隨機存取記憶體設計權重儲存及更新電路，運用在我們小組設計的突波式神經晶片系統中。

    　　Artificial intelligence is one of the hottest topics nowadays. Whether it is automotive, medical, or financial, it can be related to the word AI. The neural network is to operate the computer system in a way that mimics the human brain. Compared with traditional computers, the human brain has a strong ability to learn and infer, and the ability to recognize images or voices is far from being comparable to computers. Therefore, it is worthwhile to study the neural network that is low power consumption and can do large number of operations parallelly.

    　　In neural network, strength of synaptic connections are considered to be related to learning and memory. This thesis aims to implement synaptic plasticity circuit by memory, which can adjust the strength of synaptic connections and store the results. The former part of this thesis focuses on the measurement and discuss CRRAM, to know if it is possible to be an analog synaptic device. But the measurement results seem not great, and the tapeout of the programming circuit of CRRAM is not accepted, which is caused by DRC errors. As a result, we design SRAM circuit to store weight value and execute weight update, which is in our SNN neuromorphic chip.

    致謝 2 摘要 3 Abstract 4 Content 5 List of figures 7 List of tables 10 Chapter 1 Introduction 11 1.1 Motivation 11 1.2 Thesis Organization 12 Chapter 2 Theory Description and Literature Review 13 2.1 Spike-Timing-Dependent Plasticity 13 2.2 The introduction of Resistive Random-access Memory 14 2.2.1 Resistive Random-access Memory 14 2.2.2 Synaptic Application Using RRAM 15 2.2.3 Structure of CRRAM 16 2.3 An Asynchronous SRAM Controller 17 2.4 Summary 18 Chapter 3 The Possibility of Implementing CRRAM As an Analog Synaptic Device 19 3.1 Operation of CRRAM 19 3.2 Measurement of Voltage-Pulse Programming 21 3.3 Measurement of Current-Pulse Programming 25 3.4 Current-Pulse Programming Circuit 29 3.4.1 Architecture of Current Pulse Circuit 29 3.4.2 Simulation Results 30 3.4.3 Measurement Results 31 3.5 Conclusion 35 Chapter 4 Synaptic Weight Update Implementation 36 4.1 Architecture of Synapse Circuit 36 4.2 The SRAM Circuit 38 4.3 Asynchronous SRAM Controller 40 4.4 Weight Update Procedure 42 4.4.1 Weight Value Calculation by Combinational Logic 43 4.4.2 Peripheral Memory Circuits 44 4.4.3 Simulation Results 45 Chapter 5 Neuromorphic Chip and Future Work 49 5.1 Architecture of Spiking Neuron Network Chip 49 5.2 System Function and Simulation Results 51 5.3 Pin Definition and Layout Figure 53 5.4 Measurement Result of Weight Update Circuit 56 Chapter 6 Conclusion and Future Work 63 References 64

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    [9]Bernabé Linares-Barranco, Teresa Serrano-Gotarredona , IEEE, and Rafael Serrano-Gotarredona “Compact Low-Power Calibration Mini-DACs for Neural Arrays With Programmable Weights ” IEEE TRANSACTIONS ON NEURAL NETWORKS, VOL. 14, NO. 5, SEPTEMBER 2003
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    [13] Izhikevich, E. M., "Which Model to Use for Cortical Spiking Neurons?," IEEE Transactions on Neural Networks, vol.15, no. 5, pp. 1063-1070, 2004.

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