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研究生: 徐偉翔
Hsu, Wei-Hsiang
論文名稱: 考慮溫度限制下多核處理器之效能最佳化
Throughput Optimization for Thermally Constrained Multi-Core Processors
指導教授: 張世杰
Chang, Shih-Chieh
口試委員:
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 資訊工程學系
Computer Science
論文出版年: 2009
畢業學年度: 97
語文別: 英文
論文頁數: 40
中文關鍵詞: 多核心處理器溫度限制效能最佳化
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  • 隨著製程的進步,微電路設計中的電功耗密度會逐年增加,而電功耗密度的增加也會造成溫度的上升;為了避免溫度過高所造成的嚴重影響,在晶片設計時必須要有溫度上的限制。多核心處理器是現今常被用來增加晶片效能的架構;晶片效能可以被表示成每個核心的速度乘上權重後的加總,核心的速度愈快,效能會愈好;另一方面,從讓晶片滿足溫度限制的的角度來看,核心速度是愈慢愈好,效能最佳化就是定義成去決定每個核心的速度,讓晶片效能最好並且滿足溫度的限制。我們提出了一個效能最佳化方法,這個方法的時間複雜度是線性的,而且效能的增進比起之前研究還要好4.01%。


    Abstract 3 List of Contents: 4 List of Figures: 5 List of Tables: 6 Chapter 1 Introduction 7 Chapter 2 System-Level Thermal and Power Models 12 2.1. Thermal Model 14 2.2. Power Model 17 2.2.1. Dynamic Power Model 17 2.2.2. Leakage Power Model 17 Chapter 3 Problem Formulation 20 Chapter 4 Methodology 22 4.1. Problem of the Previous Work 23 4.2. Effective Throughput Optimization Algorithm 25 4.3. Minor Modification of the Previous Work 31 Chapter 5 Experimental Results 32 5.1. Experimental Flow 32 5.2. Experimental Results 34 Chapter 6 Conclusions 36 References 37

    [1]. S. Siddha, V. Pallipadi, and A. Mallick, “Process scheduling challenges in the era of multi-core processors,” Intel Technology Journal, vol. 11, no.4, pp.361-367, November 2007.
    [2]. J. Li and J. F. Martinez, “Power-performance considerations of parallel computing on chip multiprocessors,” ACM Trans. Archit. Code Optim., vol. 2, no. 4,pp. 397-422, 2005.
    [3]. C. Isci, A. Buyuktosunoglu, C.-Y. Cher, P.Bose, and M. Martonosi, “Analysis of efficient multi-core global power management policies: Maximizing performance for a given power budget,” in Proc. Intl’ Symp. Microarch. (MICRO), 2006, pp.347-358.
    [4]. J. Donald and M. Martonosi, “”Techniques for multicore thermal management: Classification and new exploration,“ in Proc. ISCA, 2006.
    [5]. Y. LI, B. Lee, D. Brooks, Z. Hu, and K. Skadron, “CMP design space exploration subject to physical constraints,” in Proc. Intl’ Symp. High Perf. Comp. Arch. (HPCA), 2006, pp. 15-26.
    [6]. P. Chaparro, J. Gonzalez, G. Magklis, Q. Cai, and A. Gonzalez, “Understanding the thermal implications of multicore architectures,” IEEE Trans. Parallel and Distributed Sys., vol. 18, no. 8, pp. 1055-1065, August 2007.
    [7]. R. Rao, S.Vrudhula, and C. Chakrabarti, “Throughput of multi-core processors under thermal constraints,” in Proc. Intl’ Symp. Low Power Electronics and Design (ISLPED), August 2007.
    [8]. M.-N. Sabry, “Compact thermal models for electronic systems,” IEEE Trans. Components and Packaging Technologies, vol. 26, no. 1, pp. 179–185, March 2003.
    [9]. W. Huang, S. Ghosh, S. Velusamy, K. Sankaranarayanan, K. Skadron, M. R. Stan, “HotSpot: A compact thermal modeling methodology for early-stage VLSI design,” IEEE Trans. Very Large Scale Integration Systems, vol. 14, no. 5, pp. 501-513, May 2006.
    [10]. W. Liao, L. He, and K. M. Lepak, “Temperature and supply voltage aware performance and power modeling at microarchitecture level,” IEEE Trans. Computer Aided Design, vol. 24, no. 7, pp. 1024-1053, July 2005.
    [11]. A. Chandrakasan, W. J. Bowhill, and F. Fox, Design of High-Performance Microprocessor Circuits. New York: IEEE Press, 2001.

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