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研究生: 羅億綸
Lo, Yi-Len
論文名稱: 時脈數精準的時間模型應用於快速的記憶體模擬
A Cycle Count Accurate Timing Model for Fast Memory Simulation
指導教授: 蔡仁松
Tsay, Ren-Song
口試委員:
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 資訊工程學系
Computer Science
論文出版年: 2009
畢業學年度: 97
語文別: 英文
論文頁數: 36
中文關鍵詞: 記憶體系統層級設計
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  • 在這篇論文中,我們提出了一個方法,根據時脈有線狀態機自動化地產生時脈數精準的時間模型,讓使用者可以快速的模擬記憶體執行時所花費的時脈數,使用者可以在系統設計層級可先決定使用那種記憶體,且符合所需的效能。此方法主要是發現一個現象,就是當存取記憶體的時候,都會透過該記憶體的控制器去做讀取的動作,而控制器決定了存取記憶體的程序以及動作,所以我們是利用記憶體控制器去抓出記憶體的搜尋時間,在此我們定義了時脈有線狀態機去描述記憶體控制器的程序以及細節,在演算法先靜態算出搜尋時間,動態才能決定的動作就保留下來。最後在實驗的地方得證我們模型下的時脈數是正確且快速的。


    1. Introduction 2. Related Work 3. Memory model and generation algorithm 3.1. Proposed Flow 3.2. Clocked FSM 3.3. Formal CFSM Expression 3.4. The Proposed Algorithm 3.5. A SRAM Controller example 4. Experimental results 5. Conclusion and Future Work

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