應用於三維反及閘式快閃記憶體之頁面緩衝感測電路設計

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研究生：	楊宜山 Yang, Yih-Shan
論文名稱：	應用於三維反及閘式快閃記憶體之頁面緩衝感測電路設計 Page Buffer Circuit Design for 3D BE-SONOS TFT NAND FLASH Memory
指導教授：	張孟凡 Chang, Meng-Fan
口試委員:	邱瀝毅 Chiou, Lih-Yih 洪浩喬 Hong, Hao-Chiao
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電子工程研究所 Institute of Electronics Engineering
論文出版年：	2012
畢業學年度：	100
語文別：	英文
論文頁數：	99
中文關鍵詞：	三維快閃記憶體
外文關鍵詞：	3D Flash Memory
相關次數：	點閱：139 下載：0
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在現今的半導體記憶體中，反及閘型快閃記憶體在大容量資料存取的應用中扮演最重要的腳色。由於元件面積是平面半導體記憶體中最小的，反及閘型快閃記憶體可以達成很高的元件密度，降低製造成本。傳統大容量資料存取的媒介是硬碟，必須倚靠機械裝置旋轉磁性物質來存取資料，有著高耗能與低資料吞吐量的缺點，無法應用於可攜式電子產品。反及閘型快閃記憶體不需要任何的機械裝置，近年來廣泛被應用在智慧型手機以及平板電腦等可攜式電子產品，以及固態硬碟等高速的儲存媒介上。
現今最先進的反及閘型快閃記憶體已經微縮到二十奈米，平面式的反及閘型快閃記憶體微縮越來越困難，成本越來越高，製程微縮未來將不再是可行降低成本的辦法。既然無法縮小平面上的元件，要達成更高的記憶體容量的另一條出路就是在垂直方向堆疊更多的元件。在這樣的概念下，三維的反及閘型快閃記憶體應運而生，目前被視為下一世代大容量資料存取應用的解決方案。
反及閘型快閃記憶體的隨機存取速度很慢，為了能達成高度的資料吞吐量，反及閘型快閃記憶體採取大頁面同時感測的方式，每一或兩條位元線就會搭載一組感測電路，稱為頁面緩衝器。他負責感測出數十奈安培的微小電流，轉換成數位訊號。還必須支援寫入以及抹除驗證的機制。
我們提出一種應用於七十五奈米三維垂直閘極BE-SONOS型式反及閘型快閃記憶體的頁面緩衝器。可以補償三維架構中逐層不同的臨界電壓需求且採用反向感測機制阻絕來自源極線的雜訊，另外亦可支援多次感測的機制減少位元線耦合的雜訊。

NAND Flash memory plays an important role to data storage in the modern semiconductor memory. With the smallest cell area in the planar semiconductor memory, NAND Flash memory can achieve high cell density and low cost. Conventional large capacity data storage media is hard disk driver. It needs to use the dynamic mechanical structure to rotate the magnetic disc to read and write data. This characteristic makes it hard to be used in the portable device and have the disadvantage of high power and low throughput. Recently, the NAND Flash memory is widely used in the portable electronic products such as smartphone and tablet and high performance data storage media such as Solid State Disk (SSD).
The state of art of the modern NAND Flash technology has reaching 1x nanometer node. The technology scaling has become more and more difficult and expensive. In the near future, the technology shrinking will not be the effective method to reduce the cost. In order to achieve high storage capacity, the three dimensional NAND Flash technology is regarded as the solution of the next generation large data storage application in the recent year.
The random access speed of NAND Flash memory is quite slow. To achieve high data throughput, NAND Flash memory uses large page size and simultaneous sensing. Every one or two bit lines are connected to one sensing circuit called page buffer. It needs to sense the several tens nano ampere cell current and support the program and erase verify scheme.
We proposed a page buffer circuit for 75nm 3DVG BE-SONOS NAND Flash memory. It can support layer aware verify to compensate the different threshold voltage requirement for different layer in the 3DVG structure. It uses the reverse sensing scheme to eliminate the source line noise and supports the multi-sensing scheme to reduce the BL coupling noise.

Contents
                                                   Page
    Abstract (Chinese)
    Abstract (English)
    Acknowledgements (Chinese)
A Thesis    i
Abstract    iii
Contents    vi
Page    vi
LIST OF FIGURES    ix
LIST OF TABLES    ix
Chapter 1.    Introduction    1
1    NAND Flash Memory Application    1
2    Limitation of the NAND FLASH Technology    3
3    Thesis Overview    7
Chapter 2.    3D Vertical Gate (3DVG) BE-SONOS Type NAND FLASH Memory    8
1    Bandgap Engineered SONOS (BE-SONOS) Memory Device    8
2    Array Organization    9
3    Read Operation    11
4    Program Operation    13
4.1    Fowler–Nordheim Tunneling Program    13
4.2    Self-Boost Program Inhibit (SBPI) Technique    14
4.3    Program Verify Algorithm    16
4.4    Incremental Step Pulse Programming (ISPP)    18
5    Erase Operation    19
5.1    Hole Tunneling Erase    19
5.2    Self-Boost Erase Inhibit Technique    20
5.3    Erase Verify Algorithm    21
Chapter 3.    Previous Sensing Scheme    24
1    Forward Voltage Sensing    24
1.1    Basic Concept    24
1.2    BL Interleaving Architecture    26
1.3    Example    27
2    Forward Current Sensing    29
2.1    Basic Concept    29
2.2    Multi-Sensing Method    31
2.3    Example    33
3    Reverse Voltage Sensing    35
3.1    Basic Concept    35
3.2    Example    36
Chapter 4.    Challenges of 3DVG NAND FLASH    38
1    BL Coupling Noise    38
2    Source Line Noise    42
3    Layer by Layer Vth Requirement    43
4    Background Pattern Dependency (BPD)    45
Chapter 5.    Proposed Page Buffer    46
1    Layer Aware Program Verify (LAPV)    46
2    Multi-sensing Method    48
3    Proposed Page Buffer Circuit    51
4    Read Operation    53
5    Program Verify Operation    55
6    Erase Verify    58
Chapter 6.    Analysis and Comparisons    59
1    Mathematical Analysis of Reverse Sensing    59
2    Simulation Waveform of Proposed Reverse Sensing    62
3    Noise Analysis    63
3.1    Background Pattern Dependency (BPD)    63
3.2    BL coupling noise    65
4    Latch Disturbance Problem    65
5    Comparison with other Sensing Scheme    70
5.1    Noise margin    70
5.2    Read Latency and throughput    72
5.3    Energy Consumption    77
Chapter 7.    Macro Implementation    80
1    Macro Structure    80
2    Array Organization    81
3    Periphery Circuit    82
Chapter 8.    Experiments and Conclusion    84
1    Experiments    84
1.1    Read Operation    85
1.2    Program Verify Operation    87
1.3    Layer Aware Program Verify    90
1.4    Erase Operation    91
2    Conclusions    94
3    Future Work    95
Reference    96

                                

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