橫向擴散金氧半導體功率電晶體可以同時作為輸出級電流驅動(Output Current Driver)及靜電放電防護元件，所以在應用面上相當廣泛，目前使用在薄膜液晶顯示器驅動電路 (LCD Driver)、電源管理積體電路 (Power Management IC) 和汽車電子 (Motor Electronics) 等領域。由於其可使用在高功率、高壓、高能量及高頻的電路上，所以被功率半導體積體電路廣泛地採用。隨著元件尺寸的縮小，先進的功率晶片整合技術需求上，LDNMOS 電晶體必須降低元件的特性導通電阻可大幅減少尺寸以利於微縮晶片之面積，然而提高崩潰電壓和元件可靠度的特性需求卻日益增加。
本論文研究的目的是藉由提出了三種不同結構的橫向擴散金氧半導體功率電晶體，在不改變元件操作特性、不增大尺寸與不增加額外製程步驟前提下，就原來元件布局做些微改變，來提升元件靜電放電防護能力並探討其改善機制。
這三種元件分別是圓形超高壓 (500V) 橫向擴散金氧半導體(Circular Ultra High Voltage LDNMOS) 功率電晶體與隔離式高壓 (32V) 橫向擴散金氧半導體 (Isolation LDNMOS) 功率電晶體和雙重降低表面電場高壓 (40V) 橫向擴散金氧半導體 (Double RESURF HV-LDMOS) 功率電晶體。
就圓形超高電壓橫向擴散金屬氧化物半導體 (Circular ultra-high voltage lateral diffusion MOS;C-UHV-LDNMOS) 進行人體模型靜電放電（HBM ESD）測試的故障機制進行研究並提出改善的對策，這故障機制是發生在漏極N+擴散區域，當大電流注入漏極後促使基極擴張 (Kirk effect or base push-out effect) 到N+擴散區域，由於電流擁擠效應造成電流集中在漏極N+擴散區域的邊緣；因此提出了將此漏極的單一大圓形的N+擴散區域，改成許多小圓形的N+擴散區域，如此就可以將電流分散到每一個小圓形的N+擴散區域，來避免電流集中在單一個N+擴散區域的圓週，成功提高人體模型靜電放電時大電流承受的能力。
就隔離式高壓橫向擴散金屬氧化物半導體 (High-Voltage isolated lateral diffused NMOS; HV ISO-LDNMOS) 保護環的故障機制來做為較低的電壓就可觸發其本體寄生電晶體元件的靜電放電能力進行研究與模擬；由於平板效應的影響，高壓保護環 (HVNW Guard-Ring) 到源極的崩潰電壓比本體元件的漏極到源極低，所以就模擬資料，在漏極到源極的寄生電晶體導通前，先期的靜電電流會流入高壓保護環到源極間的一個小寄生電晶體，而後增大的靜電電流會再觸發其本體寄生電晶體元件導通靜電電流；因此提出了將漏極與高壓保護環間，利用其本身結構的寄生電阻來當成串聯電阻限制高壓保護環 (HVNW Guard-Ring) 的電流來避免大電流流入高壓保護環 (HVNW Guard-Ring) 到源極端的小寄生電晶體，並提早驅動本體寄生電晶體元件導通靜電電流，來強化靜電放電的保護能力。
另一種結構的雙重降低表面電場高壓隔離橫向擴散金屬氧化物半導體 (Double RESURF HV ISO-LDMOS)，就是因為平板效應與雙重降低表面電場結構的影響，造成高壓保護環 (HVNW Guard-Ring) 到源極端的高壓PW環 (HVPW Pick-up Ring) 有較低的崩潰電壓，因此再提出將新的低電壓觸發矽控整流器 (SCR) 嵌入在高壓保護環來保護 HV ISO-LDMOS。
因此這上述研究就三種不同結構的橫向擴散金氧半導體功率電晶體，在不改變元件操作特性與不增大尺寸前提下，成功實現了原來元件布局做些微改變，就可提升元件靜電放電防護能力,且那些方法都不需增加額外的製程步驟，觸發裝置，觸發電路，和增加元件尺寸，而造成生產成本的增加。

Laterally diffused metal oxide semiconductor (LDNMOS) power transistors can simultaneously act as an output stage current drive (output current driver) and an electrostatic discharge protection device. This large flexibility has been utilized in a wide range of applications such as film liquid-crystal display drivers, power management integrated circuits (ICs) and automotive (motor) electronics because LDNMOS could drive these ICs operation at high power, high voltage, high frequency, and high energy condition. Moreover, LDNMOS transistors can be downscaled to the tiny component sizes demanded of technically advanced power chip integration, facilitating the fabrication of miniature wafers with good device characteristics (on-resistance and breakdown voltage) and high device reliability.
This thesis presents and evaluates the improve ESD robustness methodologies of three different structures of LDNMOS transistors from that the original configurations of the element's layout were slightly altered to enhance the electrostatic discharge (ESD) protection capability without changing the operating characteristics, increasing the device size, or adding new processing steps and extra trigger circuits.
　　The three different kinds of LDNMOS transistors are the circular ultra-high voltage LDNMOS transistor (C-UHV NLDNMOS); isolated HV LDNMOS (ISO-HV NLDNMOS), and double reduced-surface-field HV LDNMOS (D-RESURF HV LDNMOS). Without considering the ESD protection capabilities of these LDNMOS transistors during the process development stages, they are all very vulnerable to the ESD stress. Through the detailed insight into the investigations of the failure mechanisms, the solutions how to improve the transistor ESD performances without increasing their dimensions are proposed and developed successfully.
For C-UHV LDNMOS, the HBM (Human body model) failure is caused by the current crowds at the N+ junction edge of the drain. Instead of a large single N+ diffusion, these many small N+ diffusions are proposed to uniform the current distribution of the transistor by novel drain design engineering that eliminate the current crowding and enhance ESD performance is proposed.
For 32V HV ISO-LDNMOS device, we find that the parasitic npn bipolar between the high-voltage N-well guard ring (HVNW-GR) and source turns on before the parasitic npn bipolar between the drain and source since it has the smaller breakdown voltage . So, the transistor fails at low-voltage ESD zapping events when the HVNW-GR is connected to the drain, while it can pass the high voltage ESD zapping events when the HVNW-GR is floated.　
　　Because the breakdown voltage of the HVNW-GR is smaller than that of the drain, the HVNW-GR can be designed as the ESD protection device (SCR) to protect the D-RESURF HV LDNMOS from ESD damaging. Therefore, for 40V HV ISO-LDNMOS device, a new low-voltage triggering silicon-controlled rectifier (SCR) was proposed and embedded in the guard rings of the LDNMOS transistor. But why it cannot be conventionally embedded in the LDNMOS transistor, the reason is that the SCR embedded at drain is not suitable for the ESD protection device design of Double RESURF HV-LDNMOS at the breakdown voltage concern. Therefore, the SCR embedded in the guard (drain) rings of the LDNMOS transistor is expected to realize next-generation small-scale devices.
　　In summary, after slightly modified the in-situ layout by fewer mask, these modified LDNMOS successfully was enhanced the ESD robustness to meet the industry ESD specification (HBM 2kV and MM 200V) without degrading any their IV characteristic and increasing transistor size. Moreover, these improve methodologies have no additional processing steps, trigger circuits and extra area with increasing the production costs of the devices.　

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