進入深次微米的時代，半導體製造技術的進步使得系統單晶片(SOC)是可行的。然而，卻也帶來更多新的問題，測試就是其中的一大挑戰。更多的接腳使得探針卡(Probe Card)製作的難度提高許多，新產品的速度越來越快，也使得時間(timing)的錯誤(Fault)更加難以測試；另外，平行測試也是一個重要的課題，同時可以測試的數目越多，便可以降低測試的時間與成本。傳統的測試都是使用昂貴的測試機台來維持測試的品質以及錯誤的涵蓋率，然而，這樣的測試方法已經漸漸地無法跟上製程進步的速度了，必須要有一個突破性的測試方法。
因此，HOY的概念被提了出來，主要是根據無線測試的方法，解決傳統測試的問題。本篇論文以HOY的概念為基礎，我們先提出一個成本模型，並且合理的假設現今製程的成本，經過評估的結果，可得知在低多餘面積(Area Overhead)之下，HOY可以大幅的降低測試的成本。傳統的測試流程有許多多餘的部分，在不影響錯誤涵蓋率的前提下，我們重新提出了一個針對HOY的產品測試流程，不僅可以提昇測試的品質，亦可以降低測試的時間；我們也提出新的平行測試方法，在合理的假設之下，不僅大幅提昇了同時可測的數目，也大幅降低了測試時間達80%。最後，我們實現了一個無線測試平台，使用現今成熟的藍芽模組作為無線的傳輸器(Transceiver)，利用此平台來顯現HOY的概念。

As we enter the deep submicron age, the continuous improvement of manufacturing technologies
has made SoC possible. However, it also brings a lot of challenges in testing. Higher pin count
will make it more difficult to probe the dies on the wafer. At speed test is harder due to higher
frequency of new SoC products, making it more difficult to maintain the fault coverage and yield.
Meanwhile, higher test parallelism is still needed in mass production. Traditional test methodology
will be harder and harder to catch up with the increased speed of new process. We thus need to
develop new test methodologies to solve tomorrow’s test problems.
In the HOY project recently defined at NTHU, a wireless testing methodology is proposed.
Based on the HOY concept, we first develop economics models for both the traditional test and
HOY wireless test. We consider test cost, manufacturing cost, and development cost in cost model.
With the models and some assumptions, we show that HOY will be better than traditional test, so
far as the area overhead stays low. We also show that when the process technology continuous to
improve, HOY will gain more benefits. A new production test flow is developed to increase the
test efficiency, fault coverage and yield. We also propose a parallel testing method to reduce test
time. Using our parallel testing method in HOY, the test time will be reduced by more than 80%.
Finally, we implement an experimented wireless testing platform using the Bluetooth tool kit
and our memory BIST compiler (BRAINS). Experimental results show the feasibility of the HOY
concept.
1

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