具學習能力之隨機突波式仿神經網路分析與晶片設計

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研究生：	賴吳勳 Lai, Wu-Hsun
論文名稱：	具學習能力之隨機突波式仿神經網路分析與晶片設計 The Analysis and Implementation of Stochastic Spiking Neural Network with on-chip Learning Capability
指導教授：	陳新 Chen, Hsin
口試委員:	劉奕汶 Liu, Yi-Wen 彭盛裕 Peng, Sheng-Yu
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2020
畢業學年度：	108
語文別：	英文
論文頁數：	47
中文關鍵詞：	仿神經網路、晶片設計、機器學習
外文關鍵詞：	spiking
相關次數：	點閱：2 下載：0
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近年來，隨著機器學習的蓬勃發展，越來越多神經電路演算法被推出，應用在生活周遭，例如社群媒體、廣告投放等等，而這些神經模型的訓練往往仰賴大量的資料來進行監督式的學習，不但消耗大量的能源，也和真實的生物神經系統運作方式不太相同。然而，大腦的運作不但功耗極低，也能進行非監督式學習，亦即不需太多資料即可訓練出高準確度的資料分類能力。在研究上，發現生物神經具有隨機性之突波產生，並能夠透過這樣的現象來增強對雜訊的耐受性，除此之外，也有文獻顯示透過雜訊能幫助隨機性突波神經網路的學習。
本論文探討了隨機性突波神經網路之模擬與分析，利用軟體分析之結果來訂定神經網路電路之規格，設計並建構出具有學習能力之隨機突波式神經網路晶片。論文內容主要聚焦於：演算法重建與模擬、訂定硬體規格、突觸可塑性電路與突觸電路之電路設計。

In recent years, with the developing of machine learning, more and more algorithms of the neural networks have been proposed. The applications of the neural networks, for example, social media and advertisements, are related to our lives. However, most of the architectures are supervised systems. They are not only high power consuming, but also different from the operation of the nervous system in biology. The human brain has very strong ability of unsupervised learning and inferring with extremely low power consumption. It does not need huge amount of data as reference while learning. Some researches show that there exists stochastic behavior in biological neurons, which is helpful for enhancing the robustness to noise.
This thesis introduces the simulations and analyses of the stochastic spiking neural network. The specifications of the neural network circuit are defined by the results of the simulations. The neural network circuit can thus be designed with the specifications. The content includes simulation and reconstruction of algorithm, definition of circuit specification, Spike-Time-Dependent-Plasticity (STDP) circuit design, and synapse circuit design.

Chapter 1    Introduction------------------------------------------1
1    Motivation----------------------------------------------------1
Chapter 2    Theory description and literature review--------------2
1    Introduction of neuron models---------------------------------2
1.1    Leaky Integrate-and-Fire model--------------------------------2
1.2    Izhikevich neuron model---------------------------------------3
2    Spike time dependent plasticity (STDP)------------------------5
3    Hardware architecture of STDP circuit-------------------------6
3.1    Asymmetric decaying learning window STDP circuit--------------6
3.2    Long- and short-term weight update and storage----------------9
4    Hardware architecture of synapse circuit---------------------10
4.1    MOS transistor subthreshold current model--------------------11
4.2    Diff-Pair Integrator (DPI) synapse---------------------------11
Chapter 3    MATLAB simulation of the applied SNN-----------------14
1    Algorithm description----------------------------------------14
2    Parameters and computation in the SNN algorithm--------------16
3    Simulation result--------------------------------------------20
3.1    Simulation with Gaussian distributed images------------------20
3.2    Simulation with MNIST data-----------------------------------22
Chapter 4    Parameters mapping from MATLAB simulation to circuit design---------------------------------------------------------------25
1    Parameters mapping derivation--------------------------------25
2    Simulation result with circuit specification setting---------27
Chapter 5    The spiking neural network on chip design------------29
1    System overview----------------------------------------------29
2    Spike time dependent plasticity circuit----------------------30
3    Synapse circuit----------------------------------------------36
4    Timing control circuit---------------------------------------39
Chapter 6    Measurement result-----------------------------------40
1    Detail information of the chip-------------------------------40
2    STDP circuit-------------------------------------------------43
3    Synapse circuit----------------------------------------------45
Chapter 7    Conclusion and future work---------------------------46
References-----------------------------------------------------------47


                                

1. Gerstner, W., et al., Neuronal Dynamics. 2009.
2. Burkitt, A.N., A Review of the Integrate-and-fire Neuron Model: I. Homogeneous Synaptic Input. Biological Cybernetics, 2006. 95(1): p. 1-19.
3. Izhikevich, E.M., Simple model of spiking neurons. IEEE Transactions on Neural Networks, 2003. 14(6): p. 1569-1572.
4. Izhikevich, E.M., Which model to use for cortical spiking neurons? IEEE Transactions on Neural Networks, 2004. 15(5): p. 1063-1070.
5. Dan, Y. and M.-m. Poo, Spike Timing-Dependent Plasticity of Neural Circuits. Neuron, 2004. 44(1): p. 23-30.
6. Kang, D.-H., et al., Emulation of spike-timing dependent plasticity in nano-scale phase change memory. Neurocomputing, 2015. 155: p. 153-158.
7. Bofill-i-petit, A. and A. Murray, Synchrony Detection and Amplification by Silicon Neurons With STDP Synapses. IEEE transactions on neural networks / a publication of the IEEE Neural Networks Council, 2004. 15: p. 1296-304.
8. Indiveri, G., E. Chicca, and R. Douglas, A VLSI array of low-power spiking neurons and bistable synapses with spike-timing dependent plasticity. IEEE Transactions on Neural Networks, 2006. 17(1): p. 211-221.
9. Sharroush, S.M., Analysis of the subthreshold CMOS logic inverter. Ain Shams Engineering Journal, 2018. 9(4): p. 1001-1017.
10. Bartolozzi, C. and G. Indiveri, Synaptic dynamics in analog VLSI. Neural computation, 2007. 19: p. 2581-603.
11. Nessler, B., et al., Bayesian Computation Emerges in Generic Cortical Microcircuits through Spike-Timing-Dependent Plasticity. PLOS Computational Biology, 2013. 9(4): p. e1003037.
12. Gilson, M., T. Masquelier, and E. Hugues, STDP Allows Fast Rate-Modulated Coding with Poisson-Like Spike Trains. PLOS Computational Biology, 2011. 7(10): p. e1002231.
13. Bertsekas, D.P. and J.N. Tsitsiklis, Introduction to probability. 2008.
14. Yann, L., C. Cortes, and C.J.C. Burges. The MNIST Database of handwritten digits. Available from: http://yann.lecun.com/exdb/mnist/.
15. Nielsen, C., N. Qiao, and G. Indiveri. A compact ultra low-power pulse delay and extension circuit for neuromorphic processors. in 2017 IEEE Biomedical Circuits and Systems Conference (BioCAS). 2017.
16. Suszkiw, J.B., Chapter 32 - Synaptic Transmission, in Cell Physiology Source Book (Fourth Edition), N. Sperelakis, Editor. 2012, Academic Press: San Diego. p. 563-578.

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