連續時間三角積分調變器，由於其省電，並具有反摺疊失真濾波器的訊號轉移函數，因而被廣泛使用於單晶片系統設計中。但礙於在使用高位元數量化器的設計中，動態元件匹配電路會產生過長的延遲，同時相當耗費面積，因此限制了調變器中所使用的量化器解析度。為了提升調變器的解析度，就必須使用更高過取樣率的設計，也因此整個調變器必須操作於更高的頻率底下，進而增加整個系統的功耗。
在本論文中提出了將一階雜訊塑型概念加入一截斷部分輸出量化器中的方法。架構包含了一個三階迴路濾波器、六位元連續漸進式類比數位轉換器、三位元電流導向式數位類比轉換器與三位元動態元件匹配電路，藉由使用雜訊塑型技巧，將原本應有六位元的解析度降至三位元而不會影響調變器性能。在本設計中，藉由將動態元件匹配電路延遲由回授路徑中移除，電路可採用延遲較長卻更節省面積的架構，而一階雜訊塑型的功能，則藉由連續漸進式類比數位轉換器中的電容數位類比轉換器實現，可降低系統實現該方法所需要的硬體。
本作品使用台積電90奈米一般用途互補式金氧半製程實現，調變器的頻寬為1.92MHz，取樣頻率為61.44MHz，量測結果在輸入差動訊號為0.8V的峰對峰值底下，得到了72.2dB的訊號對雜訊失真比，而整個電路的功耗為2.92mW，整體調變器的FOM為229fJ/conv.。

Continuous-time ΣΔ modulators are popularly used in SOC due to its low power consumption and anti-aliasing filter-embedded signal transfer function. However, the quntizers’ resolution which is limited by hardware cost and extra time delay of dynamic element matching circuit. To further increase modulators resolution, higher OSR was used in conventional designs which led to high power consumption of the whole system.
In the proposed CTDSM, we construct an output-truncated SAR which has first-order noise-shaping as the quantizer in the CTDSM. The CTDSM consists of a 3rd loop filter, a 6 bits SAR ADC, a 3-bit current-steering DAC and a 3-bit DEM circuit. The 3-bit output truncated doesn’t degrade the modulator’s performance much due to the first order noise-shaping. Since the DEM function in our new arrangement is not in series of loop operation, DEM circuit with longer time delay but small area could be used. In the meanwhile, the DEM’s number of bits decrease from 6 to 3. The noise-shaped mechanism is realized by the capacitor DAC in SAR and consumes small area.
This work was realized in TSMC 90nm general purpose CMOS process. The modulators bandwidth is 1.92MHz with clock rate of 61.44MHz. The measurement result shows it achieves 72.2dB SNDR with 0.8Vpp,diff input signal. The CTDSM power consumption is 2.92mW, resulting in FOM of 229fJ/conv.

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