研究生: |
羅婉瑜 Wan-Yu Lo |
---|---|
論文名稱: |
磁性隨機存取記憶體測試與診斷演算法發展與評估 Test and Diagnosis Algorithm Generation and Evaluation for MRAM |
指導教授: |
吳誠文
Cheng-Wen Wu |
口試委員: | |
學位類別: |
碩士 Master |
系所名稱: |
電機資訊學院 - 電機工程學系 Department of Electrical Engineering |
論文出版年: | 2008 |
畢業學年度: | 96 |
語文別: | 英文 |
論文頁數: | 44 |
中文關鍵詞: | 演算法產生 、錯誤診斷 、磁性隨機存取記憶體 、記憶體測試 、寫入干擾錯誤 、權重錯誤涵蓋率 |
外文關鍵詞: | algorithm generation, fault diagnosis, magnetic random access memory (MRAM), memory testing, write disturbance fault, weighted fault coverage |
相關次數: | 點閱:3 下載:0 |
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在本論文裡主要討論磁性隨機存取記憶體的測試及診斷,首先針對磁性隨機存取記憶體(Magnetic Random Access Memory,MRAM)特有的錯誤模型-寫入干擾錯誤(Write Disturbance Fault,WDF)提出特有的偵測方法-回讀(Read-previous),並討論它對其他傳統錯誤模型偵測上的影響,另外針對不同置亂架構(Scrambling
Architecture)的磁性隨機存取記憶體也有不同的測試方法。另外我們針對磁性隨機存取記憶體提出二>個工具:磁性隨機存取記憶體錯誤模擬器(Magnetic Random Access Memory Simulator for Error
Screening,RAMSES-M)及磁性隨機存取測試及診斷記憶體演算法產生器(Test and Diagnosis Algorithm Generator by Simulation for MRAM,TAGS-M)。除了支援傳統常見的錯誤模型,RAMSES-M和TAGS-M支援回讀及權重錯誤(Weighted Fault)的觀念,我們針對寫入干擾錯誤提出權重錯誤,期冀能更準確的評估演算法的測試能力,而在本文裡同時也討論針對寫入干擾錯誤決定權重的方法。最後我們比較TAGS-M產生的演算法和傳統March演算法的測試及診斷能力,由RAMSES-M的實驗數據和實際晶片的量測數據顯示,包含回讀的演算法具有較好>的測試及診斷能力。另外,量測數據同時包含Bitmap Viewer和錯誤症狀(fault syndrome)的分佈,而這些結果也幫助我們發展更多測試方法來了解磁性隨機存取記憶體的問題。
[1] L. Savtchenko, B. N. Engel, N. D. Rizzo,M. F. Deherrera, and J. Janesky, “Method of writing to scalable magnetoresistive random access memory element”, U.S. Patent No. 6545906, Apr.
2003.
[2] T. Kai, M. Yoshikawa, M. Nakayama, Y. Fukuzumi, T. Nagase, E. Kitagawa, T. Ueda, T. Kishi, S. Ikegawa, Y. Asao, K. Tsuchida, H. Yoda, N. Ishiwata, H. Hada, and S. Tahara, “Improvement of robustness against write disturbance by novel cell design for high density MRAM”, in Proc. IEEE IEDM, Dec. 2004, pp. 583–586.
[3] J. J. Nahas, T. Andre, C. Subramanian, B. Garni, H. Lin, A. Omair, and W. Martino, “A 4Mb 0.18um 1T1MTJ toggle MRAM memory”, in Proc. IEEE Int’l Solid-State Cir. Conf.(ISSCC), Feb. 2004, pp. 44–512.
[4] D. Gogl, C. Arndt, J. C. Barwin, A. Bette, J. DeBrosse, E. Gow, H. Hoenigschmid, S. Lammers, M. Lamorey, L. Yu, T. Maffitt, K. Maloney, W. Obermaier, A. Sturm, H. Viehmann, D. Willmott, M. Wood, W. J. Gallagher, G. Mueller, and A. R. Sitaram, “A 16-Mb MRAM featuring bootstrapped write drivers”, IEEE Jour. of Solid-State Circuits, vol. 40, no. 4, pp. 902–908, Apr. 2005.
[5] C.-L. Su, R.-F. Huang, C.-W. Wu, C.-C. Hung, M.-J. Kao, Y.-J. Chang, and W.-C. Wu, “MRAM defect analysis and fault modeling”, in Proc. Int’l Test Conf. (ITC), Charlotte, Oct. 2004, pp. 124–133.
[6] C.-L. Su, C.-W. Tsai, C.-W. Wu, C.-C. Hung, Y.-S. Chen, and M.-J. Kao, “Testing MRAM for write disturbance fault”, in Proc. Int’l Test Conf. (ITC), Santa Clara, Oct. 2006.
[7] C.-L. Su, C.-W. Tsai, C.-W. Wu, C.-C. Hung, Y.-S. Chen, D.-Y. Wang, Y.-J. Lee, and M.-J. Kao, “Write disturbance modeling and testing for MRAM”, IEEE Trans. on VLSI Systems, vol. 16, no. 3, pp. 277–288, Mar. 2008.
[8] Y. Shimizu, H. Aikawa, K. Hosotani, N. Shimomura, T. Kai, Y. Ueda, Y. Asao, Y. Iwata, K. Tsuchida, S. Ikegawa, and H. Yoda, “MRAM write error categorization with QCKBD”, in Proc. IEEE Int’l Workshop on Memory Technology, Design and Testing (MTDT), Taipei, Aug. 2006, pp. 3–8.
[9] A. J. van de Goor, Testing Semiconductor Memories: Theory and Practice, ComTex Publishing, Gouda, The Netherlands, 1998.
[10] C.-F. Wu, C.-T. Huang, K.-L. Cheng, and C.-W. Wu, “Fault simulation and test algorithm generation for random access memories”, IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 21, no. 4, pp. 480–490, Apr. 2002.
[11] L.-T. Wang, C.-W. Wu, and X. Wen, Design for Testability: VLSI Test Principles and Architectures, Elsevier (Morgan Kaufmann), San Francisco, 2006.
[12] C.-F. Wu, C.-T. Huang, and C.-W. Wu, “RAMSES: a fast memory fault simulator”, in Proc IEEE In/t’l Symp. on Defect and Fault Tolerance in VLSI Systems (DFT), Albuquerque, Nov. 1999, pp. 165–173.
[13] K.-L. Cheng, J.-C. Yeh, C.-W. Wang, C.-T. Huang, and C.-W. Wu, “RAMSES-FT: A fault simulator for flash memory testing and diagnostics”, in Proc. IEEE VLSI Test Symp. (VTS), Monterey, California, Apr. 2002, pp. 281–286.
[14] C.-F. Wu, C.-T. Huang, K.-L. Cheng, and C.-W. Wu, “Simulation-based test algorithm generation for random access memories”, in Proc. IEEE VLSI Test Symp. (VTS), Montreal, Apr. 2000, pp. 291–296.
[15] J. T. de Sousa, F. M. Goncalves, and J. P. Teixeira, “Physical design of testable CMOS digital integrated circuits”, IEEE Jour. of Solid-State Circuits, vol. 26, no. 7, pp. 1064–1072, July 1991. [16] J. T. de Sousa and J. P. Teixeira, “Defect level estimation for digital ICs”, in Proc. IEEE Int’l Symp. on Defect and Fault Tolerance in VLSI Systems (DFT), Dallas, Nov. 1999, pp. 32–41.
[17] M. Durlam, P. J. Naji, A. Omair, M. DeHerrera, J. Calder, J.M. Slaughter, B. N. Engel, N. D. Rizzo, G. Grynkewich, B. Butcher, C. Tracy, K. Smith, K. W. Kyler, J. J. Ren, J. A. Molla, W. A. Feil, R. G. Williams, and S. Tehrani, “A 1-Mbit MRAM based on 1T1MTJ bit cell integrated with copper interconnects”, IEEE Jour. of Solid-State Circuits, vol. 38, no. 5, pp. 769–773, May 2003.
[18] A. J. van de Goor and Z. Al-Ars, “Functional memory faults: a formal notation and a taxonomy”, in Proc. IEEE VLSI Test Symp. (VTS), 2000, pp. 281–289.
[19] A. J. van de Goor and I. Schanstra, “Address and data scrambling: causes and impact on memory tests”, in Proc. IEEE Int’l Workshop on Electronic Design, Test, and Applications (DELTA), Christchurch, Jan. 2002, pp. 128–136.
[20] C.-F. Wu, C.-T. Huang, C.-W. Wang, K.-L. Cheng, and C.-W. Wu, “Error catch and analysis for semiconductor memories using March tests”, in Proc. IEEE/ACM Int’l Conf. on Computer-Aided Design (ICCAD), San Jose, Nov. 2000, pp. 468–471.