覆晶式技術是1964年由IBM公司開發的，覆晶式技術能有更多的I/O個數、更短的連線、更少的電力線以及更好的熱傳導等特性，這些對高效能的數位系統設計很重要。在這篇論文，我們討論在覆晶式設計中區塊與輸入輸出緩衝器擺置的問題，目的是同時的使線路延遲總和及輸入/輸出線路延遲差距總和最小化，我們提出了兩個簡單而有效的演算法來解決這個問題，兩個演算法以擺置區塊來最小化線路延遲總和及以擺置輸入輸出緩衝器來最小化線路延遲差距總和，和現有方法[5]比較，實驗結果顯示，兩個演算法能夠找到有更小線路延遲總和及線路延遲差總和為加權目標函數的擺放結果，改進率最高分別為65%和77.5%，而且執行時間快非常多，此外，當第二個演算法修改成擺放時考慮區塊和輸入輸出緩衝器旋轉，改進率變的更高，達到82.4%。最後我們延伸我們第二個演算法去解決當延遲差距變成要滿足的限制條件(取代要最小化的目標函數部分)之有限的延遲差問題，實驗結果顯示，線路延遲總和能夠進一步的改進若不考慮和考慮區塊及輸入輸出緩衝器旋轉分別高達32.8%和40%。

Flip-chip bonding was developed by IBM in 1964. Flip-chip bonding facilitates higher I/O counts, shorter interconnect routes, smaller power rails, and better thermal conductivity, all of which are important in high performance digital systems. In this thesis, we study the problem of block and I/O buffer placement in flip-chip design. The goal of the problem is to simultaneously minimize the total path delay and the total skew of all input/output signals. We present two simple yet effective algorithms for the problem. Both algorithms place blocks to minimize the total path delay, and place I/O buffers to minimize the total path skew. As compared to an existing method [5], the experimental results show that both algorithms are able to get placement solutions of smaller weighted costs of total path delay and total path skew with the improvement rates up to 65% and 77.5%, respectively, and to run much faster. Moreover, when the second algorithm is modified to consider rotations of blocks and I/O buffers as well, the improvement rate becomes even higher, up to 82.4%. Finally, we extend our second algorithm to solve the bounded skew problem where the skew becomes a constraint to satisfy (instead of a part of the cost function to be minimized). The experimental results show that the total path delay could be further reduced by up to 32.8% and 40% without and with considering rotations of blocks and I/O buffers, respectively.

[1]P. H. Buffet, J. Natonio, R. A. Proctor, Yu. H. Sun and G. Yasar, “Methodology for I/O Cell Placement and Checking in ASIC Designs Using Area-Array Power Grid,” Proc. IEEE Custom Integrated Circuits Conf. , pp. 126-128, 2000.
[2]Faraday Corp. , “Block and Input/Output Buffer Placement for Skew/Delay Minimizationin Flip-chip Design,” IC/CAD Contest Taiwan, 2003. http://www.cs.nthu.edu.tw/~cad/cad91/Problems/P3/CAD_contest_2003_P3.pdf
[3]R. Farbarik, X. Liu, M Rossman, P. Parakh, T. Basso and R. Brown, “CAD Tools for Area-Distributed I/O Pad Packaging,” Proc. IEEE Multi-Chip Module Conf. , pp. 125-129, 1997.
[4]J. N. Kozhaya, S. R. Nassif and F. N. Najm, “I/O Buffer Placement Methodology for ASICs,” Proc. IEEE International Conf. on Electronic, Circuits and Systems, pp. 245-248, 2001.
[5]C. -Y. Peng, Block and Input/Output Buffer Placement in Flip-Chip Design, Master Thesis, Institute of Electronics Engineering, National Taiwan University, 2003.
[6]C. Tan, D. Bouldinand and P. Dehkordi, “Design Implementation of Intrinsic Area Array ICs,” Proc. Conf. on Advanced Research in VLSI, pp. 82-93, 1997.