隨著硬體科技的進步，需求量日漸增加的隨身多媒體裝置以及通訊設備逐漸佔據了人們的生活，而不論是音樂或視訊的編解碼計算、音訊的過濾處理、或是電子通訊的錯誤還原…等數位訊號處理，演算法都不斷的被改進。為了能夠因應規格快速開發新的產品以搶得Time-To-Market的先機，又要保留程式本身的執行效率，有越來越多的多媒體裝置設計業者採用DSP Solution。為了在這樣的趨勢之下在世界中佔有一席之地，工研院晶片中心於2004年著手開發台灣的第一個VLIW DSP—PACDSP (Parallel Architecture Core)，冀望能夠在隨身多媒體的應用方面，提供使用者一組完整的Solution，進而成為世界最佳的開發平台。

在本論文中，我們藉由對PACDSP核心架構的研究，提出一組使我們用以評估的Algorithm Kernel能夠在PACDSP之上達到最佳效能的實作方式，其中我們以演算法的流程、在2個Cluster上的資料分割方式、實作使用的指令組合與硬體架構之間配合的關係、以及演算法的最佳化探討…等方面來進行研究，以程式設計者的觀點指出其硬體架構及指令集對於各種DSP之基本應用演算法的開發所造成的影響。並與市場上已知的DSP進行數據比較，分析PACDSP的架構與指令集對我們的實作所造成的影響，提出分析及改善建議。

With the development of silicon technology, the need of portable multimedia and communication devices is increasing fast day by day, which dominate people’s daily life. The digital signal processing algorithm, such as video and audio codec, voice filtering, and error correction, are also changing in a fast pace. To quickly develop new products with compatibility of latest specifications and algorithm without sacrificing its efficiency, more and more portable device vendors choose DSP solution. Seeing this trend, the SoC Technology Center (STC) in ITRI, started to develop the first VLIW DSP in Taiwan, called PAC (Parallel Architecture Core) DSP. The objective of PACDSP is to provide portable device vendors a complete solution, and to become the best development platform.

In this paper, through the research on PACDSP kernel architecture, we have developed an efficient implementation of the evaluating algorithm kernels. We describe our implementations on PACDSP through algorithm flows, data parallelization on both clusters, the relationship between combination of instructions and hardware architecture, and algorithm-level optimizations, from the view of software programmers. Then we compare the cycle count and code size results with the existing DSPs, analysis the impact of PACDSP kernel architectures and instruction sets on our implementations, at last we put forward our suggestions to PACDSP architecture.

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