先進的數位電路設計中，需要設計一個時鐘樹來同步時脈到達每一個儲存單元的時間，如果到達儲存單元的時間訊號無法同步，則會產生時脈偏移。時脈偏移是一個很嚴重的問題，因為時脈偏移將直接影響電路的效能及可靠度。數位電路可能會再不同的環境下運行，如不同的電源供應電壓、運行溫度…等等，或者被設計者設計成在不同的電壓模式下操作，這些多重操作模式或環境參數將影響電路的時間行為，不同的時間行為將導致不同的時脈偏移。所以要設計一個時鐘樹同時滿足每一個操作模式或環境參數下的時間行為限制是非常困難。
我們利用線性規劃演算法，針對每一個操作模式的時間行為，同時最佳化時脈偏移，得到一個最佳解。但是最佳解是線性的值，製程技術提供的電路元件可能無法達到最佳解，於是我們又提出一個演算法將電路元件的時間延遲對應到最佳解，以得到一個估計最佳的實際時鐘樹佈局。我們觀察時脈偏移其實和時間從時脈源頭到每一個儲存單元的相對差距有關，根據此特性，我們可以動態調整時脈源頭到儲存單元的時間，在對應無法到達最佳解而產生偏差時，利用之後的對應將偏差補回來，以降低因無法對應到最佳解時而產生的時脈偏移誤差。我們的方法和當今商業工具SOCEncouunter比較，達到34.34%的改進。

Clock skew optimization is a complicated problem in modern VLSI technologies because circuits often operate in many environments (corners) such as different power supply voltage and temperature or functional modes (modes) like voltage modes. While circuits operate in different corners or modes, cell delay varies a lot. It will lead to large skew variation. Therefore, to optimize clock skew in all corners or modes is very important. In this paper, we develop an approach to minimize clock skew considering multi-corner multi-mode conditions. We optimize the clock skew in all corners simultaneously by linear programming, and propose a delay mapping algorithm that maps the buffer delay of the clock tree into optimal solutions from linear programming. Our experimental results shows there are 34.34% improvement compared with the commercial tool SOC Encounter.

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