隨者半導體科技不斷演進，元件裡的漏電流越來越明顯。而當隨者元件運作一段時間，使得traps累積在氧化層並增加漏電流。也使得時依性介電崩潰變得越來越重要在現今的科技發展下。
本篇論文探討著有關閘極穿隧電流對於元件的影響及模型。為了簡化模擬，我們會用佛勒-諾德翰穿隧電流模型 (Fowler-Nordheim tunneling current model)為基礎和分析。而在這篇會假設四種穿隧電流為來簡化分析:閘極穿隧電流，閘極到汲極，閘極到源極以及閘極到通道的穿隧電流。而穿隧電流在電路上的模擬用混和(元件和電路)模擬工具。
混和模擬需要額外的資源及模擬，在現今大量電晶體的模擬並不實際。也因此，我們會需要一個簡化的模型。由簡化的電阻連接在閘極與源極以及閘極與汲極，並在第二部分希望找到簡化的電路模型來縮短模擬的時間在合理的準度下。然而，我們發現沒辦法利用這些簡化電阻來表現所提到的穿隧電流。變得需要更多的研究來建立簡化電路模型對時依姓介電崩潰模擬。

As the semiconductor technology continues to shrink, significant gate leakage current is observed, especially when the devices are under stress for a long time. In this situation, traps may accumulate in the oxide and increases the leakage current. As this time, the time dependent dielectric breakdown(TDDB) is becoming an important issue for technology development.
The goal of this thesis is to study the impact of gate tunneling current to circuit performance. For easy simulation, Fowler-Nordheim tunneling current model is applied. The 4 different locations of the tunneling current are studied: uniform across the entire gate oxide, gate to drain tunneling, gate to source tunneling and gate to channel tunneling. The impacts of theses tunneling current to circuit operation are extensively simulated using mixed level (device and circuit levels) simulation tool.
Mixed level simulations need extensive computation resources and may not be practical in circuit design with large number of transistors, thus a simplified model is sough for. It is a common practice to represent the gate tunneling current by a resistor connecting gate to source or gate to drain. The second part of the thesis tries to find such a simple transistor model to speed up simulation and with reasonable accuracy. However, it is found no such model possible with simple resistor. More researches are needed to construct the circuit level model for TDDB simulations.

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