多餘線路之加入與移除是一種改變電路結構的技術，此技術被使用在邏輯和實體設計過程中以幫助電路的合成及最佳化。此技術搜尋替代線路以替換原本電路中的目標線路而不改變整個電路的功能。對於搜尋替代線路的問題，過去的方法使用兩個步驟的演算法。首先，對於一個目標線路，先建立一個集合的候選線路。接下來，使用多餘測試以決定是否一條候選線路為替代線路。近來，一個步驟的演算法RAMFIRE被提出，此方法透過三次的邏輯蘊涵以搜尋後向替代線路，而且不需要嘗試錯誤的多餘測試。然而，相較於過去兩個步驟的演算法，此方法所能搜尋的替代線路數目較少。在這次論文中，我們提出改進的一個步驟演算法，此方法只包含兩次的邏輯蘊涵。此外，我們的方法可以搜尋前向及後向替代線路。實驗結果顯示，對於搜尋後向替代線路，我們的方法相較於RAMFIRE平均只須83%運算時間，而且可以搜尋到相同數目的替代線路。當延伸至搜尋前向及後向替代線路，我們的方法平均上可以增進157%的結果，而只須多花32%的運算時間。

Redundancy Addition and Removal (RAR) is a restructuring technique used in the synthesis
and optimization of logic designs and physical designs. It finds alternative wires to replace
a given target wire without changing the functionality of the circuit. Previous approaches
apply two-stage algorithms for this problem. First, building up a set of candidate wires for
the target wire. Second, determining if a candidate wire is an alternative wire by redundancy
test. Recently, a one-stage algorithm RAMFIRE [1] is proposed. It conducts three implications
to identify backward alternative wires without trial-and-error redundancy test. However,
the number of alternative wires it can find is smaller as compared with that obtained by the
previous two-stage approaches. In this paper, we propose an improved one-stage algorithm,
which only conducts two implications. Furthermore, both forward and backward alternative
wires are obtained by our approach. The experimental results show that as compared with
RAMFIRE for backward alternative wires, our approach only requires 83% cpu time on average,
while obtaining the same number of alternative wires. As extending to both backward and
forward alternative wires, our approach gets 157% improvement with 32% cpu time overhead
on average.

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