本論文中第一部份主要著重在矽晶圓上形成高濃度鍺 (Ge) 薄膜以及高品質的二氧化矽 (SiO2) 熱氧化層，實驗方法首先是在矽晶圓上蒸鍍鍺薄膜，並經由退火形成單晶矽鍺 (SiGe)，後續使用濕式氧化爐管形成矽鍺氧化物 (SiGeOx)，利用矽鍺氧化物在混合氣體 (forming gas) 中會還原成鍺的特性，在矽晶圓上形成高濃度鍺薄膜以及高品質閘極介電質，並藉由各種材料分析儀器探討薄膜表面與品質。
論文第二部分主要探討使用 NH3 及 N2O 等氣體處理對氧化層電性的影響，利用在第一部份形成的結構製作 NMOS 鍺電容器，並量測其閘極漏電流、電容電壓特性、磁滯特性曲線和頻率散射圖。我們發現經過NH3氮化後，雖然能夠有效的提高電容值，但是卻會惡化漏電流、增加電子陷阱 (electron trap) 等效應，然而 NH3 氮化之後如果再以 N2O 來修補鍵結，就能夠擁有有效提高電容值、較低漏電流的好處。
第三部分則是利用上述之電容器製作出高效能鍺電晶體，並對其電晶體做各種電性分析，如Vg-Id、Vd-Id、臨限電壓、接面漏電流、遷移率 (mobility) 還有次臨界擺幅 (sub-Vt swing)，利用以上參數可讓我們了解此電晶體是否能到在微縮化的過程中依舊能擁有高驅動電流。
在本次的研究中，我們利用氫氣還原氧化鍺的方式，在矽基板上製作出了單晶的鍺，並在上面長出高品質的二氧化矽當作場效電晶體的電容，另外我們透過了氮化的方式對二氧化矽做了表面處理，其中可以觀察到不但可以有效的提高電容值，也可以使的介面缺陷電荷密度有效的降低，並且不會使的磁滯或是漏電流造成惡化的情形，在以後整合高介電質材料為閘極氧化層的時候是一個很有效的處理方法。另外我們把 MOS 電容製作成場效電晶體，最後發現可以得到良好的載子遷移率或是 Id-Vd 與 Id-Vg 等電性，有助於在持續微縮下的電晶體可以維持高驅動電流的特性。

[1] J. Bardeen and W. H. Brattain, “ The Transistor, a Semiconductor Triode,” Phys. Rev., vol.71, pp. 230, 1984
[2] J. S. Kilby, “Invention of the Integrated Circuit,” IEEE Trans, Electron Devices, ED-23,648, 1976, U.S. Patent 3, 138, 743 (filed 1959, granted 1964)
[3] K. Mistry, M. Armstrong, C. Auth, S. Cea, T. Coan, T. Ghani, T. Hoffman, A. Murthy, J. Sandford, R. Shaheed, K. Zawadzki, K. Zhang, S. Thompson and M. Bohr, “Delaying Forever：Uniaxial Strained Silicon Transistors in a 90 nm CMOS Technology,” Symp. VLSI Tech. Dig.,pp. 50-51, 2004.
[4] K. C. Saraswat, C. O. Chui, T. Krishnamohan, A. Nayfeh and P. McIntyre, “Ge based high performance nanoscale MOSFETS,” Microelectronic Engineering., vol. 80, pp. 15-21, 2005.
[5] J. Welser, J. L. Hoyt, S. Takagi, and J. F. Gibbons, “Strain Dependence of the Performance Enhancement in Strained-Si n-MOSFETs,” IEDM Tech. Dig., pp.373, 1994.
[6] M. L. Lee, C. W. Leitz, Z. Cheng, A. J. Pitera, T. Langdo, M. T. Currie, G. Taraschi, and E. A. Fitzgerald, “Strained Ge Channel p-type metal-oxide-semiconductor field effect transistors grown on Si1-xGex/Si virtual substrate,” Appl. Phys. Lett., vol. 79, no. 20, pp. 3344-3346, 2001.
[7] Masashi Shima, “<100> Strained-SiGe-Channel p-MOSFET with Enhanced Hole Mobility and Lower Parasitic Resistance,” FUJITSU Sci. Tech. J., 39,1, pp.78-83, 2003
[8] F. Y. Huang, S. G. Thomas, M. Chu, K. L. Wang, and N. D. Theodore, IEDM Tech. Dig., pp. 665 , 1996.
[9] P. J. Wang, F. F. Fang, B. S. Meyerson, J. Nocera, and B. Parker, Appl. Phys. Lett., vol. 54, pp. 2698, 1989.
[10] G. G. Fountain, R. A. Rudder, S. V. Hattangady, D. J. Vitkavage, R. J.Markunas, and J. B. Posthill, “Electrical and microstructural characterization of an ultrathin silicon interlayer used in a silicon dioxide/germanium-based MIS structure,” IEEE Electron Device. Lett., vol. 24, pp. 1010–1011, 1988.
[11] Y. Wang, Y. Z. Hu, and E. A. Irene, “Electron cyclotron resonance plasma and thermal oxidation mechanisms of germanium,” J. Vac. Sci.Technol. A, vol. 12, pp. 1309–1314, 1994.
[12] O. J. Gregory, E. E. Crisman, L. Pruitt, D. J. Hymes, and J. J. Rosenberg, “Electrical characterization of some native insulators on germanium,” Mat. Res. Soc. Symp. Proc., vol. 76, pp. 307–311, 1987.
[13] D. J. Hymes and J. J. Rosenberg, “Growth and materials characterization of native germanium oxynitride thin films on germanium,” J. Electrochem. Soc., vol. 135, pp. 961–965, 1988.
[14] D. Kuzum, A. J. Pethe, T. Krishnamohan, Y. Oshima, Y. Sun, J. P. McVittie, P. A. Pianetta, P. C. McIntyre, and K. C. Saraswat, “Interface-Engineered Ge (100) and (111), N- and P-FETs with High Mobility” IEDM Tech. Dig., pp.723, 2007.
[15] R. Xie and C. Zhu, “Effects of Sulfur Passivation on Germanium MOS Capacitors With HfON Gate Dielectric, ” IEEE Electron Device. Lett., vol. 28, pp. 976–979, 2007.
[16] K. H. Kim, R. G. Gordon, A. Ritenour, D. A. Antoniads, “Atomic layer deposition of insulating nitride interfacial layers for germanium metal oxide semiconductor field effect transistors with high- k oxide/tungsten nitride gate stacks,’’ Appl. Phys. Lett. vol. 90, pp. 212104, 2007.
[17] F. A. Trumbore, “Solid solubilities of impurity elements in germanium and silicon,” Bell Syst. Tech. J., pp. 205, 1960.
[18] A. Nayfeh, C. O. Chui, K. C. Sarawat, “Effect of hydrogen annealing on heteroepitaxial-Ge layers on Si Surface roughness and electrical quality,’’ Appl. Phys. Lett., vol. 85, no. 14, pp. 2815-2817, 2004.
[19] P Zimmerman, G Nicholas, B De Jaeger, B Kaczer, A Stesmans,. L-□ Ragnarsson, D P runco, F E Leys, M Caymax, G Winderickx, K Opsomer, M Meuris2, and M M Heyns, “ High performance Ge pMOS devices using a Si-compatible process flow,’’ IEDM Tech. Dig., pp.1, 2006.
[20] H. Shang, J. 0. Chu, S. Bedell. E. P. Gusev, P. Jamison, Y. Zhang. John A. Ott, M. Copel, D. Sadana, K. W. Guarini, M. Ieong, “Selectively Formed High Mobility Strained Ge PMOSFETs for High Performance CMOS, ” IEDM Tech. Dig., pp.157, 2004.
[21] A. Nayfeh, C. O. Chui, T. Yonehara, and K. C. Saraswat, “Fabrication of High-Quality p-MOSFET in Ge Grown Heteroepitaxially on Si,” IEEE Electron Device. Lett., vol. 28, pp. 311–313, 2005.
[22] C. C. Cheng, C. H. Chien, G. L. Luo, C. H. Yang, M. L. Kuo, J. H. Lin and C. Y. Chang, “Ultrathin Si capping layer suppresses charge trapping in HfOxNy/Gemetal-insulator-semiconductor capacitors, ” Appl. Phys. Lett., vol. 90, pp. 012905, 2007.
[23] S. Joshi, C. Krug, D. Heh, H. J. Na, H. R. Harris, J. W. Oh, P. D. Kirsch, P. Majhi, B. H. Lee, H. H. Tseng, R. Jammy, J. C. Lee, and S. K. Banerjee, “Improved Ge Surface Passivation With Ultrathin SiOX Enabling High-Mobility Surface Channel pMOSFETs Featuring a HfSiO/WN Gate Stack, ” IEEE Electron Device. Lett., vol. 28, pp. 308–311, 2007.
[24] B. D. Jaeger, R. Bonzom, F. Leys, O. Richard, J. Van Steenbergen,G. Winderickx, E. Van Moorhem, G. Raskin, F. Letertre, T. Billon, M. Meuris, and M. Heyns, “Optimization of a thin epitaxial Silayer as Ge passivation layer to demonstrate deep sub-micron n- and p-FETs on Ge-On-Insulator substrates,” Microelectron. Eng., vol. 80,pp. 26–29, 2005.
[25] T. Takahashi, T. Nishimura, L. Chen, S. Sakata, K. Kita and A. Toriumi, “Proof of Ge-interfacing Concepts for Metal/High-k/Ge CMOS Ge-intimate Material Selection and Interface Conscious Process Flow, ’’ IEDM Tech. Dig., pp.697, 2007.
[26] M. M. Frank, S. J. Koester, M. Copel, J. A. Ott, V. K. Paruchuri, H. Shang, and R. Loesing, “Hafnium oxide gate dielectrics on sulfur-passivated germanium, ” Appl. Phys. Lett., vol. 89, pp. 112905, 2006.
[27] Y. H. Wu, W. J. Chen, A. Chin and C. Tsai, “The effect of native oxide on epitaxial SiGe from deposited amorphous Ge on Si,’’ Appl. Phys. Lett., vol. 74, no. 4, pp. 528-530, 1999.
[28] W. S. Liu, J. S. Chen, D. Y. C. Lie, and M.-A. Nicolet, “Ge epilayer of high quality on a Si substrate by solid-phase epitaxy,’’ Appl. Phys. Lett., vol. 63, no. 10, pp. 1405-1407, 1993.
[29] Y. H. Wu, J. R. Wu, and M. L. Wu, “Thermal gate SiO2 for Ge metal-oxide-semiconductor capacitors fabricated on Si substrate, “Appl. Phys. Lett., vol. 91, pp. 093503, 2007.
[30] X. Guo and T. P. Ma, “Tunneling Leakage Current in Oxynitride: Dependence on Oxygen/Nitrogen Content,” IEEE Electron Device. Lett., vol. 19, pp. 207–209, 1998.
[31] L. K. Han, J. Kim, G.W. Yoon, J. Yan and D.L. Kwong, “High quality oxynitride gate prepared by reoxidation of NH3-nitrided Si02dielectrics in N2O ambient,” Electronics letters., Vol. 31 No. 74, 1995.
[32] W. P. Bai, N. Lu, and D. L. Kwong, “Si Interlayer Passivation on Germanium MOS Capacitors With High-K Dielectric and Metal Gate, ” IEEE Electron Device. Lett., vol. 26, pp. 378–380, 2005.
[33] C. O. Chui , F. Ito, and K. C. Saraswat, “Nanoscale Germanium MOS Dielectrics—PartI:Germanium Oxynitrides,” IEEE Trans. Electron Devices., vol. 53, pp.1501–1508, 2006.
[34] J. P. Xu, P. T. Lai, C. X. Li, X. Zou, and C. L. Chan, “Improved Electrical Properties of GermaniumMOS Capacitors With Gate Dielectric Grown in Wet-NO Ambient,” IEEE Electron Device. Lett., vol. 27, pp.439–441, 2006.
[35] K. Martens , C. O. Chui, G. Brammertz, B. D. Jaeger, D. Kuzum, M. Meuris, M. M. Heyns, T. Krishnamohan, K. Saraswat, H. E. Maes, and G. Groeseneken, “On the Correct Extraction of Interface Trap Density of MOS Devices With High-Mobility Semiconductor Substrates,” IEEE Trans. Electron Devices., vol. 55, pp.547–556, 2008.
[36] C. O. Chui, H. Kim, D. Chi, B. Triplett, P. C. McIntyre, and K. C. Saraswat, “A sub-400 ◦C germanium MOSFET technology with high κ dielectric and metal gate,” in IEDM Tech. Dig., p. 437, 2002.
[37] B. De Jaeger, B. Kaczer, P. Zimmerman, K. Opsomer, G. Winderickx, J. van Steenbergen, E. Van Moorhem, R. Bonzom, F. Leys, C. Arena,M. Bauer, C.Werkhoven, M. Meuris, and M. Heyns, “Ge deep sub-micron high K/MG PFET with superior drive compared to Si HiK/MG state-ofthe- art reference,” in Proc. Int. SiGe Technol. and Device Meeting, pp. 32–33, 2006.
[38] H. Shang, H. Okorn-Schmidt, K. K. Chan, M. Copel, J. A. Ott,
P. M. Kozlowski, S. E. Steen, S. A. Cordes, H.-S. P. Wong, E. C. Jones,and W. E. Haensch, “High mobility p-channel germanium MOSFETswith a thin Ge oxynitride gate dielectric,” in IEDM Tech. Dig., pp. 441–444, 2002.
[39] Y. Kamata, Y. Kamimuta, T. Ino, R. Iijima, M. Koyama, and
A. Nishiyama, “Dramatic improvement of Ge p-MOSFET characteristics realized by amorphous Zr-Silicate/Ge gate stack with excellent structural stability through process temperatures,” in IEDM Tech. Dig., vol. 429, pp. 429–432, 2005.
[40] A. Ritenour, S. Yu, M. L. Lee, N. Lu, W. Bai, A. Pitera, E. A. Fitzgerald, D. L. Kwong, and D. A. Antoniadis, “Epitaxial strained germanium p-MOSFETs with HfO2 gate dielectric and TaN gate electrode,” in IEDM Tech. Dig., vol. 433, pp. 18.2.1–18.2.4, 2003.
[41] N. Wu, Q. Zhang, C. Zhu, D. S. H. Chan, A. Du, N.Balasubramanian, M. F. Li, A. Chin, J. K. O. Sin, and D.-L. Kwong, “A TaN–HfO2–Ge pMOSFET with novel SiH4 surface passivation,” IEEE Electron Device Lett., vol. 25, no. 9, pp. 631–633, 2004.
[42] M. Perego, G. Scarel, and M. Fanciulli, “Fabrication of GeO2 layers using a divalent Ge precursor,” Appl. Phys. Lett., vol. 90, pp. 162115, 2007.