近年來，由於醫學的快速發展，人類壽命得以延長。這使得生物醫學電子市
場快速成長，對於生理訊號量測系統的需求逐漸提高。在生理訊號量測系統中，
一高精密度之類比數位轉換器為一重要方塊，為了配合低速、高精密度的應用，
所以我們選擇三角積分類比數位轉換器作為資料轉換器之架構。為了配合計畫的
需求，本論文實現一可應用於生醫感測系統並處理所擷取生理訊號之三角積分調
變器。

本論文描述一個二階一位元離散時間三角積分調變器，透過TSMC 1P6M
0.18μm製程實現。使用單迴路回授架構可使得訊號轉移函數於高頻可有較佳濾
波效果，並使得調變器有較佳穩定性；運算放大器輸入級採用軌對軌架構，用以
提高於系統中之可靠度，使得積分器之輸出擺幅較大情況下，整體調變器仍可正
常運作。並於第一級積分器使用相關雙取樣技術，用來幫助降低放大器內元件不
匹配所造成的偏差並壓抑1/f雜訊。另外分別針對調變器中可能碰到之非理想效
應及系統之雜訊作分析與探討，由此得到所需之規格參數及部分電路細節之修改
。整個三角積分調變器操作在1.8V供電電壓，在20KHz的訊號頻寬、超取樣率
為256倍的情形下，所設計的調變器可以達到訊號對雜訊與諧波失真比為93.62
dB，相當於有效位元數15.26位元；整個電路的消耗功率為2.732 mW，效能指
標為1.782 pJ/conv.，核心佈局面積為668 x 278μm2。

In recent years , due to the rapid development of medical technology , human
Life is extended . This makes the rapid growth of biomedical electronic market , and
also let the needs of the physiological signals measurement systems promoted grad-
ually .A high precision analog-to-digital (A/D) converter is an important block in the
physiological signals measurement systems ; we generally choose the delta-sigma
A/D converter as the main architecture for the data converter . To be matching requ
irements for the plan , a delta-sigma modulator which is applied in the bio-sensing
system that could handle the signal capturing by the devices is implemented in this
thesis .

This thesis presents a one-bit second-order discrete-time delta-sigma modulator
(DT-ΔΣM) , and to be implemented with TSMC 0.18-μm 1P6M process . By using CIFB
architecture make the STF to have better filtering performance at high frequency ,
and make the modulator to have better stability ; the input stage of the operational
amplifier use the rail to rail architecture to raise the reliability of the system and ma-
ke the modulator still function work even though the outpu swing of the integrat-
or is larger . Also using the CDS technique in the first intergrator stage help to reduce
the offset of component mismatches and suppress the 1/f noise . The whole delta-
sigma modulator operating at 1.8V supply voltage , with 20KHz signal bandwidth ,
and oversampling ratio of 256 , the designed modulator achieved signal to noise and
distortion ratio(SNDR) of 93.26 dB , equivalent to the effective number of bits (ENOB
) 15.26 bits .The power consumption is 2.732 mW , the figure of merit (FoM) is 1.782
pJ/conv. , and the core chip area is 668 x 278μm2 .

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