快閃記憶體誕生的30年來，全世界隨著「摩爾定律」之下，不斷的追求高密度、操作更快速的記憶體， 使得記憶體在大約3年一個世代的推衍下不斷的微縮，當IC技術往奈米級推進，快閃記憶體所衍生出的問題也越來越多。因此在過去的數十年來針對快閃記憶體微縮後所遇到的問題的研究的文獻甚多，也有致力於其它的新型記憶體架構的研究，都是為了因應未來記憶體容量提升的需求。一般認為，在元件微縮後所導致的可靠度及操作干擾的問題，將會造成快閃記憶體縮小的極限。
因此，本論文中主要有兩項工作，第一、提出以缺陷輔助穿隧模型(trap assisted tunneling model) 及Poole Frenkel Effect模型為基礎，探討其在ETOX及SONOS兩種架構下資料主要的流失機制。
另一項工作則是建構出在ETOX及SONOS兩種架構下，預測資料保存能力的模型，加入一些機率的參數，利用MATLAB程式來幫助元件的模擬及預測，並提供不同記憶體之結構與操作參數改變對資料保存能力的影響。並利用模擬結果來搭配文獻中所得之量測結果以證明此模擬程式的準確性及利用模擬來討論其中元件結構變化對記憶體可靠度及縮小化極限的影響。

Flash Memories are used extensively various portable electronic products. The Moore’s law predicts that flash memory cells scale down one generation in two to three years. When IC technology scales to nanometer feature size, flash memories will face many challenges. To further increase memory density, many researchers propose new cell structure, innovative operations and array architectures on cell. However, issues on cell reliability and disturbance are generally believes to put the ultimate limit on cell size..
In this work, two major subjects are investigated. First, the basic model on the data loss in the ETOX and SONOS cells is proposed by combing the trap assisted tunneling and Poole Frenkel leakage currents.
In addition, a data retention characteristic in ETOX and SONOS cells are predicted by the model. Using a MATLAB program, the data retention characteristics for devices with various structures are estimated. This simulated result shows fairly good agreements with data reported in the literature.

參考文獻
[1] William D. Brown, Joe E. Brewer, “Nonvolatile Semiconductor Memory Technology : A Comprehensive Guide to Understanding and Using NVSM Devices,” p.6- p.9, p.47-p.50 , IEEE Press.
[2] Dov Frohman-Bentchkowsky, “A Fully Decoded 2048-Bit Electrically Programmable FAMOS Read-Only Memory,” IEEE J. Solid-State Circuits, Vol. sc-6, No. 5, p. 301, Oct. 1971.
[3] Yunheub Song, ”Highly manufacturable 90nm nor flash technology with 0.081 cm2 Cell Size,” IEEE VLSI Technology, 2003. Digest of Technical Papers.
[4] H. A. R. Wegener, A. J. Lincoln, et. at., “The variable threshold transistor, A new electrically alterable , non-destructive read-only storage device,” in IEDM Tech. Dig., Oct. 1967.
[5] Simon Tam,Ping-Keung Ko,Chenmig Hu, “ Lucky-Electron Model of Channel Hot-Electron Injection in MOSFET’s “, IEEE Transactions On Electron Devices ,Vol ED-31,No.9, September 1984
[6] Kamohara, S.; Park, D.; Hu, C, “Deep-Trap SILC (Stress Induced Leakage Current)Model For Nominal and Weak Oxide,” Reliability Physics Symposium Proceedings, 1998. 36th Annual. 1998 IEEE International , 31 March-2 April 1998 Pages : 57 – 61
[7] Ting-Kuo Kang; Ming-Jer Chen; Chuan-Hsi Liu; Chang, Y.J.; Shou-Kong Fan, ” Numerical confirmation of inelastic trap-assisted tunneling (ITAT) as SILC mechanism,” Electron Devices, IEEE Transactions on , Volume: 48 , Issue: 10 , Oct. 2001 Pages:2317 - 2322
[8] Belgal, H.P.; Righos, N.; Kalastirsky, I.; Peterson, J.J.; Shiner, R.; Mielke, N,” A new reliability model for post-cycling charge retention of flash memories ”, Reliability Physics Symposium Proceedings, 2002. 40th Annual , 7-11 April 2002 Pages:7 - 20
[9] Margaret L. French and Marvin H. White, “Scaling of Multidielectric Nonvolatile SONOS Memory Structures,” Solid-State Electronics Vol. 37, No. 20, pp.1913- 1923, 1994.
[10] Christer Svensson and Ingemar Lundström, “Trap-Assisted Charge Injection in MNOS Structures,” J. Appl. Phys., Vol. 44, No. 10, Oct. 1973.
[11] Gritsenko, V.A.; Morokov, Yu.N.; Xu, J.B.; Pridachin, N.B.; Kalinin, V.V.; Ng, A.C.; Lau, L.W.M.; Kwok, R.W.M.”, Charge transport and nature of traps in implanted silicon nitride”, Electron Devices Meeting, 1999. Proceedings., 1999 IEEE Hong Kong , 26 June 1999 ,Pages:62 – 65
[12] Tahui Wang, “ Reliability models of data retention and read-disturb in 2-bit nitride storage flash memory cells (invited paper) “ , Electron Devices Meeting, 2003. IEDM '03 Technical Digest. IEEE International , Dec. 8-10, 2003 , Pages:169 – 172
[13] Ming-Hung Chang , “Effect of Device Structure on SONOS Operation Characteristics” Jul,2003.
[14] Intel Corporation , “Intel StrataFlash Memory Technology , Application Note”, Dec 1998.
[15] Hanafi, H.I.; Tiwari, S.; Khan, I., ” Fast and long retention-time nano-crystal memory” , Electron Devices, IEEE Transactions on , Volume: 43 , Issue: 9 , Sept. 1996 ,Pages:1553 – 1558
[16] Suhail, M. , “ Effects of Fowler Nordheim tunneling stress vs. Channel Hot Electron stress on data retention characteristics of floating gate non-volatile memories ” , Reliability Physics Symposium Proceedings, 2002. 40th Annual , 7-11 April 2002 , Pages:439 – 440
[17] Manabe, Y.; Okuyama, K.; Kubota, K.; Nozoe, A.; Karashima, T.; Ujiie, K.; Kanno, H.; Nakashima, M.; Ajika, N. ,” Detailed observation of small leak current in flash memories with thin tunnel oxides” ,Semiconductor Manufacturing, IEEE Transactions on , Volume: 12 , Issue: 2 , May 1999
Pages:170 – 174
[18] C.T. Swift, G.L. Chindalore, et al., “ An Embedded 90nm SONOS Nonvolatile Memory Utilizing Hot Electron Programming and Uniform Tunnel Erase,” IEDM 2002,pp.927-930.
[19] Reisinger, H.; Franosch, M.; Hasle, B.; Bohm, T.,” A Novel SONOS Structure For Nonvolatile Memories With Improved Data Retention” , VLSI Technology, 1997. Digest of Technical Papers., 1997 Symposium on , June 10-12, 1997 , Pages:113 - 114
[20] Jiankang Bu, Marvin H. White, “Design considerations in scaled SONOS nonvolatile memory devices,” Solid-State Electronics Vol. 45, pp.113-120, 2001.
[21] Sam pan , “Nonvolatile Memory Challenges toward Gigabit and Nano-scale Era and a Nano-scale Flash Cell : PHINES “ , SSDM , Nagoya , 2002, pp.152-153