應用於行動WiMAX通訊系統之多碼率低密度同位檢查碼解碼器之設計

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研究生：	張書豪 Su-Hao Chang
論文名稱：	應用於行動WiMAX通訊系統之多碼率低密度同位檢查碼解碼器之設計 Design of Multi-Rate LDPC Decoder for Mobile WiMAX Communication Systems
指導教授：	吳仁銘 Jen-Ming Wu
口試委員:
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 通訊工程研究所 Communications Engineering
論文出版年：	2007
畢業學年度：	95
語文別：	英文
論文頁數：	67
中文關鍵詞：	錯誤更正碼、低密度同位檢查碼、通道編碼
外文關鍵詞：	Error-correcting codes, Low-density parity-check code, Channel coding
相關次數：	點閱：3 下載：0
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低密度同位檢查碼(Low-density parity check code, LDPC)最早是由Robert Gallager在1962年發表。低密度同位檢查碼屬於線性區塊碼，擁有低密度的檢查矩陣，並且被證實具有逼近向農極限(Shannon limit)的優越錯誤更正能力。在現今科技的進步下，要實現低密度同位檢查碼解碼器不再是不可能的事，並且有越來越多關於低密度同位檢查碼的研究正在進行。在現今，有許多通訊系統採用低密度同位檢查碼作為它們的通道編碼(channel coding)，如802.11n和802.16。雖然低密度同位檢查碼擁有出色的解碼性能，實現它卻從來不是一件簡單的事。在實作上仍然有許多挑戰。繞線複雜度、晶片面積與功率消耗等都是必需列入考量的面向。
在本論文中，我們提出了符合IEEE 802.16e的低密度同位檢查碼解碼器架構設計，並且比較了在使用不同解碼演算法下的解碼性能。我們發現必須在解碼性能與硬體複雜度間作取捨(trade off)。經過比較，最後我們選擇最適合的解碼演算法Layered Belief Propagation Algorithm with min-sum來實作。我們使用SystemC去更進一步驗證我們的解碼器，並且使用Synopsys Design Compiler去合成我們設計中的幾個方塊，藉此得到時間方面的資訊去估計吞吐量(throughput)。
在設計低密度同位檢查碼解碼器時，我們使用三種設計技巧: 1.支援所有IEEE 802.16e中所定義碼率之可重置架構，2.使用Benes network解決運算節點間的繞線問題，3.重新排列特定碼率檢查矩陣之行列以增進解碼效率。

Low-density parity-check codes were first introduced by Robert Gallager in the early 60’s. They are linear block codes which have sparse parity check matrices and provide performance that comes quite close to the Shannon limit. With the advanced technology, implementing LDPC code decoder is not an impossible thing and there are more and more researches on LDPC codes. There are also many communication systems adopt LDPC codes as their channel coding, such as 802.11n and 802.16e. Although LDPC codes have excellent decoding performance, realizing it is never an easy job. There still exist many challenges when implementing LDPC code decoder. The high routing complexity, large chip area and high power consumption all need to take into concerns.
In this thesis, we present architecture design, functional simulations and the comparison of decoding performance using different decoding algorithms for IEEE 802.16e LDPC decoder. We will find that there is a trade off between error-correction capability and hardware complexity. The most suitable decoding algorithm “Layered Belief Propagation Algorithm” with min-sum is chosen to implement. The proposed LDPC decoder is implemented by SystemC to do the data flow simulation and use Synopsys Design Compiler to help us to find the critical path. The timing information of Design Complier is then used to estimate the throughput.
We use three design techniques in our LDPC decoder: 1. Reconfigurable architecture for all kinds of code rates in 802.16e, 2. Use Benes network to solve routing problem between bit nodes and check nodes, 3. Reorder the model matrix when choosing specific code rates.

Chapter 1: Introduction                                    1
Chapter 2: LDPC Codes and Related Algorithms               3
    2.1 Introduction of Block codes                        3
    2.2 Message Passing Algorithm                          5
    2.3 LDPC Decoding Algorithms                           7
        2.3.1 Log-Likelihood Ratio Sum Product Algorithm   7
        2.3.2 Layered Belief Propagation Algorithm         9
        2.3.3 Min-Sum Algorithm                           10
    2.4 Soft De-mapper                                    10
    2.5 802.16e Specification for LDPC Decoder            11
Chapter 3: Architecture Design                            16
    3.1 Conventional Design                               16
        3.1.1 Fully Parallel Architecture                 17
        3.1.2 Serial Architecture                         17
        3.1.3 Partial Parallel Architecture               18
    3.2 Adopted LDPC Decoder Architecture                 19
        3.2.1 Design issues                               20
        3.2.2 Control Signal Block                        22
        3.2.3 CSM                                         26
        3.2.4 Network and Reverse Network                 28
        3.2.5 RSM                                         35
        3.2.6 PAB                                         36
        3.2.7 PCUB                                        37
        3.2.8 Iterative Decoding Procedure                38
    3.3 Overlapped Decoding Method                        39
Chapter 4: Functional Simulation                          42
    4.1 Environment of System Simulation                  42
    4.2 Estimation of Iteration Times Using Different
        Decoding Algorithm                                43
    4.3 Iteration Times Comparison between MSA and LBPA
        with min-sum                                      45
    4.4 Decoding Performance Comparison between LLR-SPA
        Under Iteration Times 8 and LBPA with min-sum
        Under Iteration Times 4                           46
    4.5 Decoding Performance Comparison between Different
        Modulation Types Using LBPA with min-sum Under
        Iteration Times 4                                 47
    4.6 Fixed-point Simulation                            48
        4.6.1 Word-length Determination                   49
        4.6.2 Decoding Performance Comparisons between
              Floating-point and Fixed-point              52
Chapter 5: SystemC Simulation                             54
    5.1 Design Flow                                       54
    5.2 SystemC Program Flow                              55
    5.3 Throughput Estimation                             57
        5.3.1 Find Critical Path                          57
        5.3.2 Throughput Estimation for
              Different Code Rates                        62
Chapter 6: Conclusions and Future Works                   64
Bibliography                                              66

                                

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