研究生: |
陳立君 Chen, Li-Chun |
---|---|
論文名稱: |
Automatic Transactor Generation for Timing-Coherent Mixed-Level Simulation 自動化生成能時序連貫地連接混和抽象層級模組模擬的轉換器 |
指導教授: |
蔡仁松
Tsay, Reng-Song |
口試委員: |
許雅三
Hsu, Yarsun 許有進 Hsu, Yu-Chin |
學位類別: |
碩士 Master |
系所名稱: |
電機資訊學院 - 電機工程學系 Department of Electrical Engineering |
論文出版年: | 2012 |
畢業學年度: | 100 |
語文別: | 英文 |
論文頁數: | 43 |
中文關鍵詞: | 自動化 、混和層級模擬 |
相關次數: | 點閱:1 下載:0 |
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為了應對日益增加的系統複雜度,系統的設計切分成很多個不同的抽象層級來針對系統各個面向做驗證,而從較高抽象層級一層一層修改至較低的抽象層級甚至是實做層級的過程中,混合抽象層級模擬廣泛的被使用著。連接混合抽象層級模組模擬的轉換器在這之中扮演著不可或缺的角色,然而,傳統的做法只著重於將連接不同層級模組的傳輸內容轉換正確,並沒有正確的處理傳輸時序的轉換,若沒有妥善模擬交易的時序,正確的平行系統行為難以被表現,以及整體系統效能測量也難以精確。本篇提出利用有限狀態機來描述模組介面傳輸的行為特徵,並且開發一演算法來自動化生成能時序連貫地連接混和抽象層級模組模擬的轉換器,以期能夠在混合層級模擬時,能正確的模擬出系統同步平行的行為。相對於傳統只考慮傳輸內容的做法,我們的方法透過控制不同層級模組的時間並且定義了在不同抽象層級之間時序表現方式不同的轉換方法,進而來對準每筆資料交易的時序,如此便能夠精確模擬平行系統行為,系統效能測量亦能非常精確。本篇實驗報告出我們的方法可以完全準確的模擬正確的交易時序,也列出傳統方法會有二十三到四十四個百分比的時序誤差。此外,我們是第一個提出能夠支援完全時序一致的混和層級模擬的轉換器。
[1] Cai, L. and D. Gajski, "Transaction level modeling: an overview", in Proceedings of the conference on Hardware/software codesign and system synthesis, 2003, pp. 19-24.
[2] Donlin, A., "Transaction level modeling: flows and use models", in Proceedings of the conference on Hardware/software codesign and system synthesis, 2004, pp. 75-80.
[3] Pasricha, S., N. Dutt, and M. Ben-Romdhane, "Extending the transaction level modeling approach for fast communication architecture exploration", in Proceedings of the Design Automation Conference, 2004, pp. 113-118.
[4] Lo, C.K. and R.S. Tsay, "Automatic generation of Cycle Accurate and Cycle Count Accurate transaction level bus models from a formal model", in Proceedings of the Asia and South Pacific Design Automation Conference, 2009, pp. 558-563.
[5] Lo, Y.-L., M.-L. Li, and R.-S. Tsay, "Cycle count accurate memory modeling in system level design", in Proceedings conference on Hardware/software codesign and system synthesis, 2009, pp. 287-294.
[6] Bombieri, N. and F. Fummi, "On the Automatic Transactor Generation for TLM-based Design Flows". in Proceedings of the Workshop on High-Level Design, Validation, and Test, 2006, pp. 85-92.
[7] Balarin, F. and R. Passerone, "Specification, Synthesis, and Simulation of Transactor Processes". IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol. 26, Issue 10, pp. 1749-1762 , 2007.
[8] Bombieri, N., N. Deganello, and F. Fummi, "Integrating RTL IPs into TLM designs through automatic transactor generation", in Proceedings of the conference on Design, automation and test in Europe, 2008, pp. 15-20.
[9] Brahme, D., The transaction-based verification methodology. 2000.
[10] Ip, C.N., A tutorial Introduction on the new systemc verification standard. 2003.
[11] Jindal, R. and K. Jain. "Verification of transaction-level SystemC models using RTL testbenches", in Proceedings of the conference on Formal Methods and Models for Co-Design, 2003, pp.199-203.
[12] TransactorWizard. [Online]. Available: http://www.sdvinc.com
[13] BusCompiler. [Online]. Available: http://www.synopsys.com
[14] Cohesive. [Online]. Available: http://www.mentor.com
[15] T. Grotker, S. Liao, and G. M. ans Si Swan. System De-sign with SystemC. Kluwer Academic Publishers, Norwell Massachusetts, 2002.
[16] Moll, H. W. M. v., H. Corporaal, et al., “Fast and Accurate Protocol Specific Bus Modeling using TLM 2.0”, in Proceedings of the conference on Design, automation and test in Europe, 2009, pp. 316-319.
[17] Abdi, S., D. Shin, et al. "Automatic communication refinement for system level design", in Proceedings of the conference Design Automation Conference, 2003, pp. 300-305.
[18] Hsu, Z.-M., J.-C. Yeh, et al. "An accurate system architecture refinement methodology with mixed abstraction-level virtual platform", in Proceedings of the Conferene on Design, Automation and Test in Europe, 2010, pp. 568-573.
[19] Passerone, R., J. A. Rowson, et al. "Automatic synthesis of interfaces between incompatible protocols", in Proceedings of Design Automation Conference, 1998, pp. 8-13.
[20] Watanabe, S., K. Seto, et al. "Protocol Transducer Synthesis using Divide and Conquer approach", in Proceedings of the Asia and South Pacific Design Automation Conference, 2007, pp. 280-285.
[21] Open Core Protocol International Partnership (OCP-IP), www.ocpip.org.
[22] D. Flynn. “AMBA: enabling reusable on-chip designs”, IEEE Micro, 1997, pp. 20-27.