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研究生: 陳立君
Chen, Li-Chun
論文名稱: Automatic Transactor Generation for Timing-Coherent Mixed-Level Simulation
自動化生成能時序連貫地連接混和抽象層級模組模擬的轉換器
指導教授: 蔡仁松
Tsay, Reng-Song
口試委員: 許雅三
Hsu, Yarsun
許有進
Hsu, Yu-Chin
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年: 2012
畢業學年度: 100
語文別: 英文
論文頁數: 43
中文關鍵詞: 自動化混和層級模擬
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  • 為了應對日益增加的系統複雜度,系統的設計切分成很多個不同的抽象層級來針對系統各個面向做驗證,而從較高抽象層級一層一層修改至較低的抽象層級甚至是實做層級的過程中,混合抽象層級模擬廣泛的被使用著。連接混合抽象層級模組模擬的轉換器在這之中扮演著不可或缺的角色,然而,傳統的做法只著重於將連接不同層級模組的傳輸內容轉換正確,並沒有正確的處理傳輸時序的轉換,若沒有妥善模擬交易的時序,正確的平行系統行為難以被表現,以及整體系統效能測量也難以精確。本篇提出利用有限狀態機來描述模組介面傳輸的行為特徵,並且開發一演算法來自動化生成能時序連貫地連接混和抽象層級模組模擬的轉換器,以期能夠在混合層級模擬時,能正確的模擬出系統同步平行的行為。相對於傳統只考慮傳輸內容的做法,我們的方法透過控制不同層級模組的時間並且定義了在不同抽象層級之間時序表現方式不同的轉換方法,進而來對準每筆資料交易的時序,如此便能夠精確模擬平行系統行為,系統效能測量亦能非常精確。本篇實驗報告出我們的方法可以完全準確的模擬正確的交易時序,也列出傳統方法會有二十三到四十四個百分比的時序誤差。此外,我們是第一個提出能夠支援完全時序一致的混和層級模擬的轉換器。


    1. Introduction 2. Related Work 3. The Proposed Approach 3.1. Timing coherence 3.2. Local clock wrapping 3.3. Dynamic timing matching 4. Transactor Generation 4.1. Complementary FSM 4.2. Automatic generation algorithm 5. Case Study 6. Conclusion

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