多個時脈域(Multiple-Clock-Domain, MCD)的設計方法，在現今
的系統單晶片(system-on-chip, SoC)設計當中已是一種趨勢，使用
多個時脈域的設計技巧，可以有效的使整個系統單晶片的效能與消耗
功率達到最佳化，然而在多個時脈域的設計下，資料在不同時脈域之
間互相傳送的完整性以及可靠度將變得非常重要。在這篇論文中，我
們提出一個適用於 AMBA AHB 匯流排的多個時脈域的設計方法，用以
確保資料傳輸的完整性，在提出的方法之中，一個介面電路可以直接
使用於匯流排當中，而不需要更動到原來的設計，在我們的介面電路
中包含了交握(handshaking)機制，用以確保資料在不同時脈域傳送
時的完整性，另外也使用了雙正反器(Double Flip-Flop)的同步化技
巧，以解決非同步輸入訊號對電路所造成的問題，即Metastibility
的問題，此外針對AES 加解密處理器也提出一個FIFO 架構的同步化
方法，使其也能操作在不同的時脈域以達到其效能的最佳化，在這個
方法中我們主要是使用雙埠記憶體(Dual-port RAM)來暫存需要跨越
不同時脈域的資料，使用雙埠記憶體可以確保資料傳送時的完整性，
在我們的實驗結果顯示整體效能在RSA 加解密處理器上，效能大約可
提升一倍，在AES 加解密處理器的效能上，也能提升25%。

Multiple-clock-domain (MCD) based a System-on-Chip (SoC) is the trend in modern ICs. With proper use of the technique of MCD, performance and power can be effectively optimized. In this thesis, we propose an MCD design methodology for the Advanced High-Performance Bus (AHB) of the Advanced Micro-controller Bus Architecture (AMBA) system. In the proposed methodology, a wrapper is developed for the AHB bus without any modification of the original core. Our wrapper adopts a handshaking mechanism, so we can guarantee that there is no data loss when communication is done between two different clock domains. In addition, the double flip-flop synchronization method is adopted in our wrapper to avoid the metastability problem. We also propose a FIFO synchronizer for some special architecture design, e.g. the AES engine developed in our lab. A dual-port RAM is
included to safely pass data across two clock domains. In our experiment, the hardware cost of the wrapper circuit is about 2.7K gates, while it can double the throughput of the RSA function by our MCD design. The FIFO synchronizer improves 25\% performance for the AES engine.

[1] Semiconductor Industry Association, “International technology roadmap for semiconductors (ITRS), 2001 edition”, Dec. 2001.
[2] S. Hauck, “Asynchronous design methodologies: An overview”, Jan. 1995, vol. 83, pp. 69–93.
[3] W. J. Dally and J. W. Poulton, Digital Systems Engineering, Cambridge University Press, Upper Saddle River, N.J., 1998.
[4] H. J.M. Veendrick, “The behaviour of flip-flops used as synchronizers and prediction of their failure rate”, Apr. 1980, vol. 15, pp. 169–176.
[5] K. Y. Yun and A. E. Dooply, “Pausible clocking-based heterogeneous systems”, Dec. 1999, vol. 7, pp. 482–488.
[6] K. Y. Yun and R. P. Donohue, “Pausible clocking: a first step toward heterogeneous systems”, in Computer Design: VLSI in Computers and Processors, 1996, pp. 118–123.
[7] T. Chelcea and S. M. Nowick, “Robust interfaces for mixed-timing systems with application to latency-insensitive protocols”, in Design Automation Conference, 2001, pp. 21–26.
[8] T. Chelcea and S. M. Nowick, “Robust interfaces for mixed-timing systems”, in Very Large Scale Integration (VLSI) Systems, 2004, pp. 857–873.
[9] A. Peeters and K. v. Berkel, “Single-rail handshake circuits”, in Asynchronous Design Methodologies, 1995, pp. 53–62.
[10] C. E. Cummings, “Synthesis and scripting techniques for designing multi-asynchronous clock designs”, www.sunburst-design.com/papers, 2001.
[11] Inc. Cadence Design Systems, “Clock domain crossing”, http://www.cadence.com/, 2004.
[12] Altera, FLEX 8000 Embedded Programmable Logic Device Family Data Sheet, Ver. 10.01, Altera, Co., June 1999.
[13] C. Dike and E. Burton, “Miller and noise effects in a synchronizing flip-flop”, June 1999, vol. 34, pp. 849–855.
[14] National Institute of Standards and Technology (NIST), Data Encryption Standard (DES), National Technical Information Service, Springfield, VA 22161, Oct. 1999.
[15] C.-P. Su, Design and Test of an Advanced Cryptographic Processor, PhD dissertation, Dept. Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan, June 2004.
[16] Inc. ARM Components, AMBA Specification Rev2.0, May 1999.
[17] C.-L. Horng, “An aes cipher chip design using on-the-fly key scheduler”, Master Thesis, Dept. Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan, June 2004.
[18] M.-Y. Wang, C.-P. Su, C.-T. Huang, and C.-W. Wu, “An HMAC processor with integrated SHA-1 and MD5 algorithms”, in Proc. Asia and South Pacific Design Automation Conf. (ASP-DAC), Yokohama, Jan. 2004, pp. 456–458.
[19] C.-H. Wang, C.-P. Su, C.-T. Huang, and C.-W. Wu, “A word-based RSA crypto-processor with enhanced pipeline performance”, in Proc. 4th IEEE Asia-Pacific Conf. Advanced System Integrated Circuits (AP-ASIC), Fukuoka, Aug. 2004, pp. 218–221.
[20] C. E. Cummings and D. Mills, “Simulation and synthesis techniques for asynchronous fifo design”, www.sunburst-design.com/papers, 2002.