摘要
以純鍺本身對矽而言，電子遷移率提升兩倍至於電洞可以提升至四倍，但是由於鍺的能隙相對於矽來的小(0.67 eV)，在常溫下不容易量測到準確的界面陷阱能量分佈，對於鍺電晶體元件而言，低溫量測變成一個勢在必行的量測方法。
為了提升鍺基板元件的特性，一層高品質的界面層是需要的。本研究使用四種不界面層搭配不同電漿處理之元件，其界面層分別為(GeO2(H2O plasmna)、GeON(O2+NH3 plasma)、GeON(H2O+NH3 plasma)、AlON(H2O+NH3 plasma))，並搭配high-k材料Al2O3作為高介電氧化層，製作成電晶體。為了分析不同製程方式形成界面層之元件界面層缺陷，論文首先介紹電荷汲引技術(charge pumping)的基本原理與量測方法，藉由載子的捕捉與複合得到之淨電流，稱為汲引電流(Icp)。將不同的汲引電流換算後可得到對應的界面陷阱密度與能量分佈狀況，以及得到邊緣陷阱密度與空間分佈的關係。
論文中第一部份介紹常溫下鍺電晶體界面特性與基本電特性，界面特性方便包括界面缺陷Nit、界面陷阱能量分佈Dit、邊緣陷阱密度縱深分佈Nbt，常溫下發現GeON(O2+NH3 plasma)作為界面層之元件其界面特性最為優秀，平均Dit最低，此外透過邊緣陷阱密度配合TEM圖可以觀察到元件之界面層厚度很薄其厚度約0.7 nm，而在載子遷移率方面，四種不同界面層之元件載子遷移率皆有很好表現。
接著比較常溫(300 K)與低溫(233 K)基本電性與界面特性。由於鍺能隙較小(0.67 eV)，從基本電性Id-Vg圖與Gp-Vg圖顯示在低溫時明顯抑制載子之產生效應，其代表低溫效應對鍺電晶體元件在電性上有顯著的影響，另外在界面特性方面，從界面陷阱能量分佈圖可以發現低溫時較靠近能隙邊緣缺陷密度容易被量測出來；靠近價帶的缺陷數量與常溫時差不多，而靠近導帶的缺陷數量則較常溫時大，從邊緣陷阱密度縱深分佈圖可以發現常溫下與低溫下缺陷分佈趨勢相當，其代表靠近界面的缺陷在低溫下容易被量測出來而遠離界面之缺陷則較不易被量測出來，較不受低溫影響。
最後一部分為不同製程方式形成界面層低溫下界面特性與定電壓電應力下可靠度分析。由結果可以看出低溫下較能響應出靠近能隙邊緣缺陷密度，同樣以GeON(O2+NH3 plasma)作為界面層之元件界面特性與可靠度最佳，低溫時載子遷移率與常溫時皆有很好表現且趨勢與常溫下雷同。在可靠度方面同樣以GeON(O2+NH3 plasma)作為界面層之元件受定電壓電應力之後臨界電壓飄移量最低。此外不同製程方法成長界面層之元件其而受定電壓電應力之後界面缺陷增生幾乎都在10%以下，其界面增生行為較為不明顯，界面品質較為優秀。

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