HOY 無線測試平台基頻收發機之設計與實現｜國立清華大學博碩士論文庫

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研究生：	張介銘 Chieh-Ming Chang
論文名稱：	HOY 無線測試平台基頻收發機之設計與實現 Design and Implementation of a Baseband Transceiver for HOY Wireless Test Platform
指導教授：	馬席彬 Hsi-Pin Ma
口試委員:
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2007
畢業學年度：	95
語文別：	中文
論文頁數：	92
中文關鍵詞：	巴克碼、取樣頻率漂移、維特比、無線測試、收發機、基頻
外文關鍵詞：	Barker code, Sampling frequency offset, Viterbi, Wireless test, Transceiver, Baseband
相關次數：	點閱：2 下載：0
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在本篇論文中，包含設計基頻封包及規格，功能的模擬，架構設計和邏輯設計，最後實作基頻收發機到場效式可程式閘陣列FPGA 板，並被整合及應用於 HOY 無線測試平台。
首先本論文提出一個適合無線測試的基頻規格的設計，其中基頻封包設計以巴克碼(Barker code)為核心設計碼，為了搜尋射頻 (RF) 載波頻率的三次交握協定 (handshake) 以及和媒體存取控制 (MAC) 模組及射頻模組的交換訊號協定。
接著本論文提出的基頻收發機包含以下功能模組: 介面模組、發送模組、封包偵測、封包內資料邊界偵測、取樣頻率漂移補償、解展頻以及維特比 (Viterbi) 解碼器。介面模組為控制與 MAC 層及 RF 層有關之訊號，封包偵測、封包內資料邊界偵測及解展頻部份以匹配濾波器概念實作，而取樣頻率漂移補償器為利用展頻特性做取樣時間點的選擇，最後 Viterbi 解碼器是以分支度量單元 (BMU) 、加-比較-選擇單元 (ACSU) 及路徑回朔單元(TBU) 的設計架構。以上均實作在FPGA板上，被應用在測試系統的測試機台 (ATE) 端以及待測晶片 (DUT) 端。
為了驗證被提出的設計，論文中以白色高斯雜訊作為通道模型。並與IEEE 802.15.4及ECMA-368等短距離無線傳輸標準所規定的系統效能做頻估，在訊號雜訊比 (SNR) 6 dB時可達到 1.2% 的封包錯誤率 (PER)。
在電路設計上，以使用簡單硬體架構並在不同的功能模組間做基本電路元件的共用以節省面積。最後本基頻收發機被整合進入無線測試頻台的展示晶片中，透過國家晶片中心 (CIC)，使用台積電 0.18μm製程製造。

In this thesis, baseband speci‾cation design, functional simulation, architecture def-
inition, and logic design along with FPGA implementation of the baseband transceiver
for HOY wireless test platform are presented.
A suitable physical layer speci‾cation is designed for wireless test. There is a hand-
shaking scheme for locking the carrier frequency of radio frequency (RF) module. Addi-
tionally, the signal protocol to exchange information with media access control (MAC)
module is also presented.
The proposed baseband transceiver includes several functional parts, interface mod-
ule, transmitter, packet detection, boundary detection, sampling frequency o®set (SFO)
compensator, despreader, and Viterbi decoder. The functional parts choose suitable
existing algorithms to implement for the functionalities of them. The implementation
is also in automated test equipment (ATE) and device under test (DUT).
Additive white Gaussian noise (AWGN) channel is used to estimate the baseband
performance. Then the proposed baseband transceiver is veri‾ed by FPGA and inte-
grated into the test platform.
Finally, an integrated demo chip has been tap-out with the baseband inside. The
chip will be measured in this summer.

Introduction 1
1 IC Test Wirelessly . . . . . . . . . . . . . . . . . . . . . . . . 1
2 HOY Wireless Test System . . . . . . . . . . . . . . . . . . . . . . . . . . 2
3 Motivation of the Thesis . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
4 Organization of the Thesis . . . . . . . . . . . . . . . . . . . . . . . . . . 4
System Descriptions 7
1 HOY System Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.1 PHY Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2 Proposed Baseband Speci‾cations . . . . . . . . . . . . . . . . . . . . . . 9
2.1 PHY Packet Format . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2 Preamble Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.3 Pilot Field and Data Field . . . . . . . . . . . . . . . . . . . . . . 13
3 Forward Error Correction . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.1 Convolutional Encoder . . . . . . . . . . . . . . . . . . . . . . . . 15
4 RF Link Handshaking Scheme . . . . . . . . . . . . . . . . . . . . . . . . 16
5 ATE and DUT Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 17
5.1 Interface with MAC Layer . . . . . . . . . . . . . . . . . . . . . . 17
5.2 Interface Signal with RF Module . . . . . . . . . . . . . . . . . . 24
5.3 Initial Block - Handshaking Scheme . . . . . . . . . . . . . . . . . 25
5.4 Data Transceiver Block - Data Mode . . . . . . . . . . . . . . . . 29
iv CONTENTS
Architecture Design 35
1 Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2 ATE and DUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
4.1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . 38
4.2 Packet Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
4.3 Boundary Detection . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.4 Despreading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4.5 SFO O®set Compensator . . . . . . . . . . . . . . . . . . . . . . . 42
4.6 Viterbi Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Channel Simulation 49
1 Baseband Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
1.1 AWGN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
1.2 Packet Error Rate . . . . . . . . . . . . . . . . . . . . . . . . . . 51
1.3 Bit Error Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Logic Design 57
1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
2 Wireless Link Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
2.1 Finite State Machine . . . . . . . . . . . . . . . . . . . . . . . . . 60
3 Interface Between Baseband and MAC Layer . . . . . . . . . . . . . . . . 61
4 Channel Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
4.1 Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
4.2 Viterbi Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
5 FSK Carrier Frequency Lock Control . . . . . . . . . . . . . . . . . . . . 66
6 Area Reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
6.1 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
CONTENTS v
Implementation and Measurement Results 75
1 FPGA Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
2 Implementation V1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
3 Implementation V2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
3.1 Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
3.2 8051 and PL2303 . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
3.3 MAC Layer and Protocol . . . . . . . . . . . . . . . . . . . . . . . 79
3.4 Baseband . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
3.5 RF Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
3.6 Result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
4 Chip Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Future Work and Conclusions 85
1 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

                                

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