對於有電量限制應用的裝置，如:物聯網裝置(IOT)、獵能裝置(energy harvesting device)以及穿戴式裝置等，屬於僅在短時間內運作，但有長時間的待機，通常需要進行動態電源調整，甚至將裝置中部分的晶片進行關機的程序降低待機時的能量消耗。現今主流的方式是使用靜態記憶體(SRAM)搭配非揮發-記憶體的組合，藉由靜態記憶體達到快速的運算，並透過非揮發-記憶體讓資料可以在關機後仍繼續被保存。但此種採用兩巨集晶片乎相搭配的方式(SRAM+NVM 2-marco solution)受到了晶片之間傳輸的介面限制，使得資料儲存至非揮發-記憶體晶片的時間過長並且造成大量的傳輸能量耗損。因此透過將SRAM與NVM整合成一顆記憶體單元的方式稱之為非揮發-靜態記憶體(nvSRAM) 被提出，透過位元間平行傳輸資料的方式，使得無須透過額外的傳輸介面，就能進行資料儲存與恢復，達成開機耗時更短、能量消耗更省的成效，帶給可攜式裝置更好的選擇。
本次研究提出了一顆由6顆電晶體組成的SRAM、搭配兩顆具有高臨界電壓特性的電晶體以及1顆電容元件(8T1C)組合而成的非揮發-靜態記憶體，並且達成了1)通過指使用一顆電容元件以及只使用一個儲存週期減少了儲存能耗，2)藉由資料電壓抬升以及初始化與覆寫的操作達成了高恢復良率，以及減少了資料恢復耗能。本次提出的8T1C非揮發-靜態記憶體單元透過使用65nm的製程建構了1個512b的8T1C非揮發-靜態記憶體測試晶片，並在測試模式獲得量測的結果，證實了此記憶體單元的可行性。

Battery-limited chip, such as IoT devices, wearable and Energy harvesting device, use the 2-macro (SRAM+NVM) solution which employ SRAM for computing and nonvolatile memory (NVM) for power-off storage to reduce standby current. Unfortunately, this solution cannot achieve frequent power-off operation, against SRAM at sleep-mode using a low supply-voltage (VDD), due to large energy usage and slow store (power-off) and restore (power-on) operations caused by the word-by- word serial transfer of data.
Nonvolatile SRAMs (nvSRAM), which perform bit-to-bit parallel data transfer between SRAM and NVM devices within a single cell, are capable of block-level parallel data transfer with faster and more energy efficient store/restore operations than are 2-macro schemes.
This study proposes a 8T1C nonvolatile SRAM (nvSRAM) to 1) reduce store energy by using a single capacitor device and one cycle store, 2) achieves high restore yield by using a date voltage boost and initialization and conversion scheme. We fabricated a 512b 8T1C nvSRAM test macro by using 65nm process. The measurement results are obtained by the test pattern and confirming the feasibility of this 8T1C nvSRAM cell.

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