對稱性輸入的偵測對於科技對應、邏輯合成及邏輯驗證而言，是一項重要的技術。之前的方法大都是經由建造BDD並發展演算法來處理這個問題。對於設計沒有相對應的BDDs或是布林函式而言，此種以BDD為基礎的方法，是不能被應用的。為了避免採用BDD為基礎的方法時遇到上述的限制，以模擬為基礎的方法已經被研究出來。這種方法可以適用在以任何層次描述法所設計的電路，尤其適用於以高階層次及黑盒子的設計。然而，之前採用模擬為基礎的方法，大多專注在處理非等價的對稱性輸入。在這篇論文，我們提出一個以模擬為基礎的方法來偵測等價對稱性輸入。經由實驗在一系列的ISCAS-85及MCNC的測試程式，證實了我們方法的有效性。

Symmetry input identification is an important technique in technology mapping, logic synthesis, and . Previous approaches deal with this problem by building BDD and developing algorithms to determine symmetric inputs. For the design whose corresponding BDDs cannot be built, BDD-based approaches cannot be applied on this problem. To avoid the limitations of BDD-based approach, simulation-based methods have been proposed. It is applicable to arbitrary level design description, especially to high level and black box design description. Previous simulation-based approaches focus on determining nonequivalence symmetry. In this paper, we propose a simulation-based approach to identify equivalence symmetric inputs. The experimental results on a set of ISCAS-85 and MCNC benchmarks demonstrate the effectiveness of our algorithm.

[1] C.-L Chou, C.-Y Wang, G.-W Lee, and J.-Y Jou, “Graph automorphism-based algorithm for determining symmetric inputs,” in Proceedings of IEEE International Conference on Computer Design, pp. 417-419, 2004.
[2] A. Mishchenko, “Fast computation of symmetries in Boolean functions,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 22, pp. 1588-1593, Nov. 2003.
[3] E. J. McCluskey, “Detection of group invariance or total symmetry of a Boolean function,” Bell System Technology Journal, pp. 1445-1453, Nov. 1956.
[4] E. J. McCluskey, Logic Design Principles with Emphasis on Testable Semicustom Circuits, Prentice-Hall, 1986.
[5] I. Pomeranz and S. M. Reddy, “On determining symmetries in inputs of logic circuits,” in Proceedings of IEEE International Conference on Computer-Aided Design, pp. 500-507, 1993.
[6] C. Scholl, D. Moller, and P. Molitor, “BDD minimization using symmetries,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 18, pp. 81-100, Feb. 1999.
[7] F. Somenzi, “CUDD: CU Decision Diagram Package, Release 2.3.1,” University of Colorado at Boulder, 2001.
[8] C.-C. Tsai and M. Marek-Sadowska, “Generalized Reed-Muller forms as a tool to detect symmetries,” IEEE Transactions of Computers, vol. 45, pp. 33-40, Jan. 1996.
[9] C.-Y Wang, S.-W Tung, and J.-Y Jou, "On Automatic Verification Pattern Generation for SoC with Port Order Fault Model", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 21, pp. 466-479, Apr. 2002.
[10] K.-H. Wang and J.-H. Chen, “Symmetry Detection for Incompletely Specified Functions with K-Disjointness Paradigm,” in Proceedings of the IEEE Asia and South Pacific Design Automation Conference, vol. 2, pp. 994-997, 2005.
[11] K.-H. Wang and J.-H. Chen, “Symmetry detection for incompletely specified functions,” in Proceedings of IEEE Design Automation Conference, pp. 434-437, 2004.