雖然SiC擁有優越的材料特性，但是SiC MOSFETs仍然面臨著低通道電子遷移率的問題，導致有較高的導通電阻。主要原因為當碳化矽藉由熱氧化製程形成SiO2過程中，部分C原子會堆積在界面處形成缺陷，導致SiC MOS元件會有較高的界面能態密度DIT影響導通特性。為了解決這個問題，一般會使用NO、N2O進行氧化後退火來降低DIT。本論文利用全面性Si離子佈植技術於SiC表面，希望藉由表面的Si離子與非晶態的碳化矽晶體來改善氧化製程，減少界面處C原子相關的缺陷並降低DIT。為了探討Si離子佈植對MOS元件的影響，本論文會使用nMOSCap、LV-nMOSFET與1.2kV的VDMOS來評估元件特性，例如VTH、S.S.、通道電子遷移率、DIT等隨離子佈植劑量的變化，也對VDMOS的崩潰特性作討論，並且利用EDX與XPS量測來分析氧化層界面的材料特性。最後討論Si離子佈植對閘極氧化層可靠度的影響，例如Hysteresis、BTI以及TDDB，也評估了在高壓脈衝量測下，VDMOS於高達1.2kV的動態RON特性。

Although SiC has superior material characteristics, SiC MOSFETs still face the issue of low channel mobility, resulting in high channel resistance. The main reason is that when thermal oxidation process is utilized for SiC to form SiO2, some of the C atoms will accumulate at the interface and form defects, which makes the SiC MOS devices have a high interface state density DIT that affects the conduction characteristics. In order to address these problems, NO and N2O are generally used for post-oxidation annealing to decrease DIT.
This paper uses a blanket Si implantation technique on the SiC surface, aiming to improve the oxidation process by means of introducing Si ions and amorphouszing SiC crystal, possibly reducing C related defects at interface and decreasing DIT. In order to explore the effects of Si implantation on the MOS devices, this paper uses nMOSCap, LV-nMOSFET and 1.2kV VDMOS to evaluate the performance, such as VTH, S.S., channel mobility, and DIT with various implantation doses. In addition, breakdown characteristics of the VDMOS are also discussed, and the material properties of the interface are analyzed using EDX and XPS measurements. Finally, the influence of Si implantation on the reliability of the gate oxide is discussed, such as Hysteresis, BTI, and TDDB. The dynamic RON under a high voltage pulse up to 1.2kV are also evaluated for VDMOS.

[1] C. M. Zetterling, “Process Technology for Silicon Carbide Device,” EMIS processing series IEEE, 2002.
[2] G. R. Fisher and P. Barnes, “Towards a unified view of polytypism in silicon carbide,” Philosophical Magazine B, vol. 61, no. 2, pp. 217-236, 1990.
[3] A. R. Powell and L. B. Rowland, “SiC Materials—Progress, Status, and Potential Roadblocks,” Proceedings of the IEEE, vol. 90, no. 6, pp. 942-955, June 2002.
[4] K. C. Chang, N. T. Nuhfer, L. M. Porter, and Q. Wahab, “High-carbon concentrations at the silicon dioxide–silicon carbide interface identified by electron energy loss spectroscopy,” Applied Physics Letters, vol. 77, no. 14, pp. 2186-2188, 2000.
[5] H.-F. Li, S. Dimitrijev, H. B. Harrison, and D. Sweatman, “Interfacial characteristics of N2O and NO nitrided SiO2 grown on SiC by rapid thermal processing,” Applied Physics Letters, vol. 70, no. 15, pp. 2028-2030, 1997.
[6] G. Y. Chung, C. C. Tin, J. R. Williams, K. McDonald, R. K. Chanana, R. A. Weller, S. T. Pantelides, L. C. Feldman, O. W. Holland, M. K. Das, and J. W. Palmour, “Improved inversion channel mobility for 4H-SiC MOSFETs following high temperature anneals in nitric oxide,” IEEE Electron Device Letters, vol. 22, no. 4, pp. 176-178, 2001.
[7] T. Kimoto, Y. Kanzaki, M. Noborio, H. Kawano, and H. Matsunami, “Interface Properties of Metal–Oxide–Semiconductor Structures on 4H-SiC {0001} and (11-20) Formed by N2O Oxidation,”
Japanese Journal of Applied Physics, vol. 44, no. 3, pp. 1213-1218, 2005.
[8] M. Noguchi, T. Iwamatsu, H. Amishiro, H. Watanabe, K. Kita, N. Miura, “Channel engineering of 4H-SiC MOSFETs using sulphur as a deep level donor,” IEEE International Electron Devices Meeting (IEDM), pp. 185-188, 2018.
[9] M. Noguchi, T. Iwamatsu, H. Amishiro, H. Watanabe, K. Kita, N. Miura, “Improvement in the Channel Performance and NBTI of SiC-MOSFETs by Oxygen Doping,” IEEE International Electron Devices Meeting (IEDM), pp. 482-485, 2019.
[10] A. J. Lelis, R. Green, D. B. Habersat, M. El, “Basic Mechanisms of Threshold-Voltage Instability and Implications for Reliability Testing of SiC MOSFETs,” IEEE Transactions on Electron Devices, vol. 62, no. 2, pp. 316-323, 2015.
[11] A. J. Lelis, D. Habersat, R. Green, A. Ogunniyi, M. Gurfinkel, J. Suehle, N. Goldsman, “Time Dependence of Bias-Stress-Induced SiC MOSFET Threshold-Voltage Instability Measurements,” IEEE Transactions on Electron Devices, vol. 55, no. 8, pp. 1835-1840, 2008.
[12] R. Singh, A. R. Hefner, “Reliability of SiC MOS devices,” Solid-State Electronics, vol. 48, no. 10-11, pp. 1717-1720, 2004.
[13] A. K. Agarwal, S. Seshadri, L. B. Rowland, “Temperature dependence of Fowler-Nordheim current in 6H- and 4H-SiC MOS capacitors,” IEEE Electron Device Letters, vol. 18, no. 12, pp. 592-594, 1997.
[14] K. Fujihira, N. Miura, K. Shiozawa, M. Imaizumi, K. Ohtsuka, T. Takami, “Successful Enhancement of Lifetime for SiO2 on 4H-SiC by N2O anneal,” IEEE Electron Device Letters, vol. 25, no. 11, pp. 734-736, 2004.
[15] M. Gurfinkel, J. C. Horst, J. S. Suehle, J. B. Bernstein, Y. Shapira, K. S. Matocha, G. Dunne, R. A. Beaupre, “Time-Dependent Dielectric Breakdown of 4H-SiC/SiO2 MOS Capacitors,” IEEE Transactions on Device and Materials Reliability, vol. 8, no. 4, pp. 635-641, 2008.
[16] T. Kimoto, J. A. Cooper, “Fundamentals of Silicon Carbide Technology: Growth, Characterization, Devices, and Applications,” John Wiley & Sons, Singapore Pte. Ltd., pp. 195, 2014.
[17] J. A. Cooper, JR., “Advances in SiC MOS Technology,” Physica Status Solidi (A), vol. 162, no. 1, pp. 305-320, 1997.
[18] S. Harada, R. Kosugi, J. Senzaki, W. J. Cho, K. Fukuda, K. Arai, S. Suzuki, “Relationship between channel mobility and interface state density in SiC metal–oxide–semiconductor field-effect transistor,” Journal of Applied Physics, vol. 91, no. 3, pp. 1568-1571, 2002.
[19] J. N. Shenoy, G. L. Chindalore, M. R. Melloch, J. A. Cooper, JR., J. W. Palmour, K. G. Irvine, “Characterization and optimization of the SiO2/SiC metal-oxide semiconductor interface,” Journal of Electronic Materials, vol. 24, no. 4, pp. 303-309, 1995.
[20] A. V. Penumatcha, S. Swandono, J. A. Cooper, “Limitations of the High - Low C-V Technique for MOS Interfaces With Large Time Constant Dispersion,” IEEE Transactions on Electron Devices, vol. 60, no. 3, pp. 923-926, 2013.
[21] R. Degraeve, B. Kaczer, G. Groeseneken, “Degradation and breakdown in thin oxide layers : mechanisms, models and reliability prediction,” Microelectronics Reliability, vol. 39, no. 10, pp. 1445-1460, 1999.
[22] J. C. Fothergill, “Estimating the cumulative probability of failure data points to be plotted on Weibull and other probability paper,” IEEE Transactions on Electrical Insulation, vol. 25, no. 3, pp. 489-492, 1990.
[23] T.-L. Wu, Long term stability of enhancement mode GaN power devices. PhD thesis, Faculty Eng., Katholieke Univ., Leuven, Belgium, 2016.
[24] L. C. Yu, G. T. Dunne, K. S. Matocha, K. P. Cheung, J. S. Suehle, K. Sheng, “Reliability Issues of SiC MOSFETs : A Technology for High-Temperature Environments,” IEEE Transactions on Device and Materials Reliability, vol. 10, no. 4, pp. 418-426, 2010.
[25] J. McPherson, V. Reddy, K. Banerjee, H. Le, “Comparison of E and 1/E TDDB models for SiO2 under long-term/low-field test conditions,” IEEE International Electron Devices Meeting (IEDM), pp. 171-174, 1998.
[26] H. Yoshioka, T. Nakamura, T. Kimoto, “Accurate evaluation of interface state density in SiC metal-oxide-semiconductor structures using surface potential based on depletion capacitance,” Journal of Applied Physics, vol. 111, no. 1, pp. 014502-1-014502-5, 2012.
[27] M. Gurfinkel, H. D. Xiong, K. P. Cheung, J. S. Suehle, J. B. Bernstein, Y. Shapira, A. J. Lelis, D. Habersat, N. Goldsman, “Characterization of Transient Gate Oxide Trapping in SiC MOSFETs Using Fast I–V Techniques,” IEEE Transactions on Electron Devices, vol. 55, no. 8, pp. 2004-2012, 2008.
[28] G. Rescher, G. Pobegen, T. Aichinger, T. Grasser, “On the subthreshold drain current sweep hysteresis of 4H-SiC nMOSFETs,” IEEE International Electron Devices Meeting (IEDM), pp. 276-279, 2016.
[29] C.-T. Yen, C.-C. Hung, H.-T. Hung, C.-Y. Lee, L.-S. Lee, Y.-F. Huang, and F.-J. Hsu, “Negative bias temperature instability of SiC MOSFET induced by interface trap assisted hole trapping,” Applied Physics Letters, vol. 108, no. 1, pp. 012106-1-012106-4, 2016.
[30] T.-L. Wu, J. Franco, D. Marcon, B. D. Jaeger, B. Bakeroot, S. Stoffels, M. V. Hove, G. Groeseneken, “Toward Understanding Positive Bias Temperature Instability in Fully Recessed-Gate GaN MISFETs,” IEEE Transactions on Electron Devices, vol. 63, no. 5, pp. 1853-1860, 2016.
[31] M. Meneghini, I. Rossetto, C. D. Santi, F. Rampazzo, A. Tajalli, A. Barbato, M. Ruzzarin, M. Borga, E. Canato, E. Zanoni, and G. Meneghesso, “Reliability and failure analysis in power GaN-HEMTs: An overview,” IEEE International Reliability Physics Symposium (IRPS), pp. 3B-2.1-3B-2.8, 2017.
[32] D. J. DiMaria, E. Cartier, and D. Arnold, “Impact ionization, trap creation, degradation, and breakdown in silicon dioxide films on silicon,” Journal of Applied Physics, vol. 73, no. 7, pp. 3367-3384, 1993.
[33] U. Schwalke, M. Polzl, T. Sekinger, M. Kerber, “Ultra-thick gate oxides: charge generation and its impact on reliability,” Microelectronics Reliability, vol. 41, no. 7, pp. 1007-1010, 2001.
[34] R. C. Hughes, “Hole mobility and transport in thin SiO2 films,” Applied Physics Letters, vol. 26, no. 8, pp. 436-438, 1975.