近年來於高介電材料和砷化銦鎵等高載子遷移率通道的金屬半導體（金氧半）場效電晶體之研究已經變得相當重要，尤其是在互補式金氧半元件的高速低耗能應用方面。一個有低缺陷密度且可有效地控制的高介電材料和砷化銦鎵的界面層是未來三五族半導體能被應用於現今以矽為主的元件的一個重要因素。本工作最重要的貢獻是利用多種電性量測的方法，如電荷幫浦的電流分析、准靜態電容電壓量測與計算、變溫的電導電壓量測分析以及深部能階暫態頻譜分析，有系統地得到一致且合理的能帶缺陷密度圖，並且製作出元件來印證他們對於元件工作表現的重要關聯。
高介電材料和砷化銦鎵的異質結構能有一個低密度且平坦的界面能帶缺陷圖，可以使我們有效地操控砷化銦鎵元件。利用分子束磊晶方式先成長砷化銦鎵磊晶層，再接續成長氧化鎵氧化釓的稀土氧化物於砷化銦鎵之上，我們除成功製作出電子元件，且也量測得到一個平坦且低密度的界面能帶缺陷密度圖。此外，我們也成功製作出單純成長氧化釓於砷化銦之上的金氧半元件，並量測獲得此界面能帶缺陷密度圖。這些結果皆可看出界面能帶缺陷密度圖對於其元件工作表現的重要影響。
除了利用分子束磊晶方式在超高真空環境下成長高介電材料外，基於元件成長製程的靈活性及成本考量，原子層沉積高介電材料接受到更多關注。常用的樣品製作流程是先利用化學製品將砷化銦鎵的表面鈍化（因砷化銦鎵已暴露於大氣中），而後再成長原子層沉積高介電材料於其上；然而此流程會限制爾後在製作元件時元件本身的熱力學穩定性。我們提議的流程是先利用分子束磊晶方式先成長砷化銦鎵磊晶層，再接續於超高真空環境下直接成長原子層沉積高介電材料，如氧化鉿或氧化鋁；此原件經過測試可有更高的熱力學穩定性，且元件的界面能帶缺陷密度更低於前者所製作出的樣品，說明了這是一個更有效的元件成長製作流程。從界面能帶缺陷密度圖的分析和Ｘ射線光電子能譜的相互關聯中，我們推測在砷化銦鎵下半部的能隙中，其界面缺陷密度的大小和多餘的砷相關鍵結有密切關係。

Recent studies on MOS field-effect transistors (MOSFETs) using high-k dielectrics on InGaAs have become essential to high-speed low-power logic applications for keeping down scaling of complementary metal-oxide-semiconductor technologies. A well controlled high-k/InGaAs interface with low interface trap densities (Dit’s) is one of the key factors for the III-V implementation to the present Si-based devices. The major achievement in this work is to obtain consistent and valid energy distribution of Dit’s [Dit(E)] by various electrical techniques, and to address its impact on MOSFETs device performance. Moreover, a speculation about possible defect states responsible for high Dit’s within the energy band gap is proposed and under discussion.
A flat energy distribution of Dit’s within the InxGa1-xAs band gap, as the U shape spectrum for SiO2/Si, is essential for effective control of the Fermi level to efficiently manipulate the device. We have performed a nearly flat Dit distribution with no discernible peak near the mid-gap region for In0.2Ga0.8As passivated by the molecular-beam-epitaxy (MBE) deposited Ga2O3(Gd2O3) [GGO] rare-earth oxide. (kGGO~14, kSi~3.9) Moreover, InAs MOS devices were also demonstrated to perform the effective passivation of Gd2O3 on III-Vs since Gd2O3 is known to be the key dielectric layer formed near the interface with InGaAs, when the mixed oxide GGO was evaporated from a Gd3Ga5O12 garnet source. Both the fabrication of depletion- and enhancement-mode MOSFETs enables the significance of obtained Dit results on the device performance.
Besides the high-k GGO deposited by the MBE approach under an ultra high vacuum environment, atomic-layer-deposited (ALD) high-k dielectrics have received much attention with the advantages of uniformity and conformality for the fabrication process flexibility. Here we directly deposited ALD oxides (HfO2, Al2O3) on pristine InxGa1-xAs (x=0.2, 0.53) surface without any chemical surface treatments, and electrical interface characterizations showed that the mid-gap and lower-half-band-gap Dit’s are obviously lower for ALD-HfO2 than Al2O3. Note that no additional Arsenic related states were detected (below the level of in-situ Xray photoemission spectroscopy detection) in the former. Nevertheless, the Dit(E) for ALD-HfO2 on In0.2Ga0.8As still exhibits a small mid-gap peak feature, implying other defect states, such as Gallium related states, may also contribute to the mid-gap Dit’s. For ALD-HfO2 on In0.53Ga0.47As with lower Gallium content, the Dit(E) shows a downward profile from the valence band to the conduction band with no mid-gap peak. The results in the so-called in-situ ALD approach appreciably compare well with those prevalent cases utilizing the HCl or (NH4)2S treatment on In0.53Ga0.47As prior to the high-kdeposition, manifesting the excellent high-k/InxGa1-xAs interface by the promising in-situ approach.

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