晶片內網路架構是一種具彈性和伸縮性的基礎架構，因為其特性使得晶片內網路架構在多核心系統的設計中變得相當重要。晶片內網路架構中是由許多路由器來連結不同的核心，因為不同核心溝通時必須透過路由器來傳遞資料，所以資料傳遞路徑上的路由器個數越多，所帶來的延遲也相對的比較長。當晶片內網路的架構越來越大時，大量的路由器和緩衝器也會造成大量的功率消耗。動態電壓和頻率的調整技術可以為晶片內網路架構節省功率消耗。在本文中，我們設計了一個低延遲且低成本的緩衝器，該緩衝器用來當作不同頻率間溝通的介面。為了讓大家明白資料傳輸延遲與動態調整頻率的晶片內網路架構之間的關係，我們提供一個快速的內網路晶片時序模擬器，藉由蟲洞傳輸、封包傳輸路徑之間的關係以及緩衝器的特性，我們可以快速的計算出每一個封包到達目的地所需要的時間。我們的晶片內網路時序模擬器會考慮到實際晶片內網路架構硬體的特性，也會考慮封包在硬體上傳輸所需的延遲時間，所以我們計算出來的時間十分精確。根據我們最後實驗數據顯示，我們的晶片內網路時序模擬器計算出來的結果和時脈精確模型所模擬的結果一模一樣，並且我們晶片內網路時序模擬器所需的模擬時間相對於時脈精確模型來的短，我們的晶片內網路時序模擬器最快可以比時脈精確模型快上96倍。

Network-on-Chip (NoC) has become an essential interconnect technology for many-core systems because of its scalable and flexible infrastructure. However, the router-based NoC structure has long latency (large hops) between connected cores. Also, large power consumption is spent on
routers and FIFOs. To address the later issue (for lower power), a Dynamic Voltage and Frequency Fcaling (DVFS) scheme is proposed for traditional NoC.
In this thesis, we first designed a low-cost low-latency synchronous FIFO to support DVFS in NoC. Then, in order to better understand the impact of latency introduced by NoC (and DVFS at lower frequency), we proposed a quick timing
simulator for DVFS NoC.
The simulator can take several important factors of a NoC into account: worm-hole switching, inter-traffic relations and speed difference between FIFOs.
In the experiment, the proposed simulator can correctly calculate all timings with a speedup up to 95 times as
compared with a cycle-accurate model.

[1] Ling Wang, Jianye Hao, and FeixuanWang, “Bus-Based and NoC Infrastructure Performance
Emulation and Comparison”, Information Technology: New Generations (ITNG) 6th Inter-
national Conference, pp. 855–858, 2009.
[2] L. Benini and G. De Micheli., “Networks on chips: a new SoC paradigm”, IEEE Computer
vol.35 no.1, p. 70.
[3] J. Henkel, W. Wolf, and S. Chakradhar, “On-chip networks: a scalable, communication-
centric embedded system design paradigm”, International Conference on VLSI De-
sign(ICVD), 2004.
[4] S.R. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh,
T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, “An
80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS,” Solid-State Circuits”, IEEE
Journal of Solid-State Circuits (JSSC), 2008.
[5] S. Bell, B. Edwards, J. Amann, R. Conlin, K. Joyce, V. Leung, J. MacKay, M. Reif, Liewei
Bao, J. Brown, M. Mattina, Chyi-Chang Miao, C. Ramey, D. Wentzlaff, W. Anderson,
E. Berger, N. Fairbanks, D. Khan, F. Montenegro, J. Stickney, and J. Zook, “TILE64 - Proces-
sor: A 64-Core SoC with Mesh Interconnect”, IEEE Journal of Solid-State Circuits (JSSC),
2008.
[6] Dean Truong, Wayne Cheng, Tinoosh Mohsenin, Zhiyi Yu, Anthony Jacobson, Gouri
Landge, Michael Meeuwsen, Christine Watnik, Anh Tran, Zhibin Xiao, Eric Work, Jeremy
Webb, Paul Mejia, and Bevan Baas, “A 167-Processor Computational Platform in 65 nm
CMOS”, IEEE Journal of Solid-State Circuits (JSSC), 2009.
50[7] A. B. Kahng, Bin Li, Li-Shiuan Peh, and K. Samadi, “ORION 2.0: A fast and accurate
NoC power and area model for early-stage design space exploration”, Proceedings of Design,
Automation and Test in Europe, pp. 423–428, 2009.
[8] A. Chakraborty and M. R. Greenstreet, “Efficient self-timed interfaces for crossing clock
domains”, International Symposium on Asynchronous Circuits and Systems (ASYNC), pp.
78–88, May 2003.
[9] A. T. Tran, D. N. Truong, and B. M. Baas, “A GALS many-core heterogeneous DSP plat-
form with source-synchronous on-chip interconnection network”, ACM/IEEE International
Symposium on Networks-on-Chip (NoCS), pp. 214–223, May 2009.
[10] A. M. Rahmani, P. Liljeberg, J. Plosila, and H. Tenhunen, “Developing reconfigurable FIFOs
to optimize power/performance of Voltage/Frequency Island-based networks-on-chip”, Inter-
national Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS),
pp. 105–110, 2010.
[11] E. Beigne, F. Clermidy, S. Miermont, and P. Vivet, “Dynamic Voltage and Frequency Scaling
Architecture for Units Integration within a GALS NoC”, ACM/IEEE International Sympo-
sium on Networks-on-Chip (NoCS), pp. 129–138, 2008.
[12] Fernando Moraes, Ney Calazans, Aline Mello, Leandro Moller, and Luciano Ost, “HERMES:
an infrastructure for low area overhead packet-switching networks on chip”, Integration, and
the VLSI Journal, pp. 69–93, 2004.
[13] E. Pekkarinen, L. Lehtonen, E. Salminen, and T. D. Hamalainen, “A set of traffic models for
Network-on-Chip benchmarking”, System on Chip (SoC), 2011 International Symposium on,
pp. 78–81, 2011.
[14] L. Lehtonen, E. Salminen, and T. D. Hamalainen, “Analysis of modeling styles on Network-
on-Chip simulation”, NORCHIP, pp. 1–4, 2010.
[15] T.-S. Su, “A DVFS Many-core ESL Simulation Platform with Software Communication
API”, Master’s thesis, National Tsing-Hua University, Electrical Engineering Department,
2012.
51[16] L. Ost, F. G. Moraes, L. Moller, L. S. Indrusiak, M. Glesner, S. Maatta, and J. Nurmi, “A
simplified executable model to evaluate latency and throughput of networks-on-chip”, Sym-
posium on Integrated Circuits and System Design (SBCCI), pp. 170–175, 2008.
[17] Lionel M. Ni and Philip K. McKinley, “A survey of wormhole routing techniques in direct
networks”, Computer, IEEE, vol.26, no.2,, pp. 62–76, 1993.
[18] Khalid M. Al-Tawil, Mostafa Abd-El-Barr, and Farooq Ashraf, “A survey and comparison of
wormhole routing techniques in a mesh networks”, Network, IEEE, vol.11, no.2,, pp. 38–45,
March-April 1997.
[19] Arteris S.A., NoC Solution 1.16 NoCcompiler User’s Guide, Feb. 2009.
[20] Arteris S.A., NoC Solution 1.16 NoCexplorer User’s Guide, Feb. 2009.
[21] Arteris S.A., NoC Solution 1.16 NoC Transaction and Transport Protocol Technical Refer-
ence, Feb. 2009.
[22] Arteris S.A., NoC Solution 1.16 OCP Network Interface Units Technical Reference, Feb.
2009.
[23] Arteris S.A., NoC Solution 1.16 Packet Transport Units Technical Reference, Feb. 2009.
[24] Ginosar, “Metastability and Synchronizers: A Tutorial”, Design & Test of Computers, IEEE,
pp. 23–35, Sept-Oct 2011.
[25] Clifford E. Cummings, “Synthesis and Scripting Techniques for Designing Multi-
Asynchronous Clock Designs”, Sunburst Design, Inc, 2001.
[26] Tarik Ono and Mark Greenstreet, “A Modular Synchronizing FIFO for NoCs”, Networks-on-
Chip, NoCS 2009. 3rd ACM/IEEE International Symposium on, pp. 224–233, May 2009.
[27] T. Chelcea and S.M. Nowick, “A low-latency FIFO for mixed-clock systems”, VLSI, 2000.
Proceedings. IEEE Computer Society Workshop on, pp. 119–126, 2000.
52[28] I. Miro Panades and A. Greiner, “Bi-Synchronous FIFO for Synchronous Circuit Communi-
cation Well Suited for Network-on-Chip in GALS Architectures”, Networks-on-Chip, NOCS
2007. First International Symposium on, pp. 83–94, May 2007.
[29] A.-M. Rahmani, P. Liljeberg, J. Plosila, and H. Tenhunen, “Developing reconfigurable FI-
FOs to optimize power/performance of Voltage/Frequency Island-based networks-on-chip”,
Design and Diagnostics of Electronic Circuits and Systems (DDECS), 2010 IEEE 13th Inter-
national Symposium on, pp. 105–110, 2010.
[30] “NanGate FreePDK45 Generic Open Cell Library”,
http://www.si2.org/openeda.si2.org/projects/nangatelib.
[31] Intel GmbH, Intel MPI Benchmarks: User Guide and Methodology Description.