符合晶片匯流排規格之正反向離散小波轉換的可參數化矽智財產生器

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研究生：	張智淳 Chih-Chun Chang
論文名稱：	符合晶片匯流排規格之正反向離散小波轉換的可參數化矽智財產生器 A Parameterized On-Chip-Bus-Compliant FDWT/IDWT Accelerator IP Generator
指導教授：	林永隆 Youn-Long Lin
口試委員:
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 資訊工程學系 Computer Science
論文出版年：	2004
畢業學年度：	92
語文別：	英文
論文頁數：	48
中文關鍵詞：	JPEG2000 、離散小波轉換、矽智財、單晶片系統晶片
外文關鍵詞：	JPEG2000, DWT, SIP, SOC
相關次數：	點閱：2 下載：0
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中文摘要

我們在這篇論文中提出一個不同參數係數的離散小波轉換硬體加速器產生器。除了在JPEG2000規格中使用的(5,3)和(9,7)濾波器，其他的濾波器像是(9,3),(6,10)和(2,2)也都可產生。這樣將來有不同應用需要使用到離散小波轉換，都可以以此產生器來快速產生。

所產生的離散小波轉換矽智財可做正向及反向的離散小波轉換。並且我們對於其效能以及耗電功率做最佳化。以此架構作為其他不同濾波器架構的基礎。接著我們分析lifting-based離散小波轉換的特性，針對各種不同係數的濾波器做分解，並且設計其相對應的架構。

我們也提供符合晶片匯流排規格(AMBA)的介面和對應的驅動程式來做系統晶片(SOC)整合。對於矽智財的介面，可能會因為不同的系統，而有不同的需求。因此我們提供了兩種介面，以中央控制器(CPU)傳送資料，另一種則是使用直接記憶體讀取(DMA)和中斷機制(interrupt)配合使用，以期達到最佳效果。

另外我們在系統晶片平台上實際整合我們的矽智財到JPEG2000應用程式。實驗結果展示了我們的矽智財產生器的確能有效得改進矽智財設計的效率。

We propose a generator for hardware acceleration of Discrete Wavelet Transform (DWT) with various coefficient parameters. Not only (5, 3) and (9, 7) DWT filters defined in the JPEG2000 image compression standard but also other filters, such as (9, 3), (6, 10) and (2, 2), can also be generated. The generated DWT IP can perform both forward and inverse transform (FDWT and IDWT). Our generator also provide on-chip-bus interface compliant with AMBA protocol and associated device driver so that the generated IPs are ready for SOC integration. We verify the proposed approach by integrating generated IPs into an SOC platform running JPEG2000 application software. Experimental results demonstrated that the proposed approach is indeed effective in enhancing the productivity of hardware accelerator IP design.

Contents
ABSTRACT    I
CONTENTS    II
LIST OF FIGURES    IV
LIST OF TABLES    V
CHAPTER 1    6
INTRODUCTION    6
CHAPTER 2    9
PREVIOUS WORK    9
CHAPTER 3    12
PROPOSED DWT ARCHITECTURE    12
3.1    DWT TOP ARCHITECTURE    12
3.1.1    COMBINE FORWARD DWT AND INVERSE DWT    12
3.1.2    THE BIT PRECISION    14
3.2    LOW-POWER AND HIGH-PERFORMANCE DESIGN    15
3.2.1    IMPROVED SYMMETRIC EXTENSION MODULE    15
3.2.2    CANONIC SIGNED DIGIT (CSD) MULTIPLIERS    18
3.2.3    USING RETIMING TO IMPROVE PERFORMANCE    20
CHAPTER 4    21
GENERALIZED DWT    21
4.1    LIFTING-BASED DWT THEORY    22
4.2    THE FACTORIZATION OF DIFFERENT WAVELET FILTERS    23
4.2.1    The factorization of odd taps wavelet filters    23
4.2.2    The factorization of even taps wavelet filters    25
4.2.3    The factorization of inverse discrete wavelet transform    26
4.3    GENERALIZED DWT ARCHITECTURE    27
4.3.1    Top local DWT architecture    27
4.3.2    Predict/Update module    28
4.3.3    Signal extension module    30
4.3.4    Control unit module    31
CHAPTER 5    32
DWT IP IMPLEMENTATION    32
5.1    SYNTHESIS RESULT    33
5.2    DESIGN-FOR-TEST SYNTHESIS REPORT AND ATPG RESULT    33
5.3    IP QUALIFICATION    34
5.4    DESIGN MODELS    34
5.4.1   Programmable parameter    35
5.4.2   Reconfigurable parameter    36
CHAPTER 6    37
VERIFICATION AND INTEGERATION    37
6.1    TESTBENCH    37
6.2    BUS INTERFACE    38
6.3    ADVANCE BUS INTERFACE    39
6.4    DEVICE DRIVER    40
6.5    A HW/SW CO-DESIGN JPEG2000    40
6.6    EXPERIMENT REPORT    41
CONCLUSIONS    44

                                

Bibliography

[1] S. Mallat, “A theory for multiresolution signal decomposition: the wavelet representation,“ IEEE Transactions on Pattern Anal. Machine Intell., Vol.11, pp. 674-693 ,July 1989.
[2] M. Vishwanath, “The Recursive Pyramid Algorithm for the Discrete Wavelet Transform,” IEEE Trans. on Signal Processing, vol. 42, no. 3, pp.673-676, Mar 1994.
[3] C.-Y. Chen, Z.-L. Yang, T.-C. Wang and L.-G. Chen, ” A programmable VLSI architecture for 2-D discrete wavelet transform,” IEEE International Symposium on Circuits and Systems 2000, Vol.1, pp. 619 – 622, May 2000.
[4] C.-T. Huang, P.-C. Tseng and L.-G. Chen, “Efficient VLSI architectures of lifting-based discrete wavelet transform by systematic design method,” IEEE International Symposium on Circuits and Systems 2002, Vol.5, pp. 565 – 568, May 2002.
[5] I. Daubechies and W. Swelden, “Factoring wavelet transform into lifting steps,” The Journal of Fourier Analysis and Applications, Vol. 4, pp.247-269, 1998.
[6] C. Chrysafis and A. Ortega, “Line-based, reduced memory, wavelet image compression,” IEEE Transactions on Image Processing, Vol.9, No.3, pp. 378-389, Mar 2000.
[7] P.-C. Wu and L.-G. Chen, “An efficient architecture for two-dimensional discrete wavelet transform,” IEEE Transactions on Circuits and Systems for Video Technology, Vol.11, No. .4 , pp. 536-545, April 2001.
[8] ISO/IEC. ISO/IEC 15444-1. Information technology – JPEG2000 Part I. image coding system. Mar 2000.
[9] C.-J. Lian, K.-F. Chen, H.-H. Chen and L.-G. Chen, “Lifting based discrete wavelet transform architecture for JPEG2000,” IEEE International Symposium on Circuits and Systems 2001, Vol.2, pp. 445 – 448, May 2001.
[10] P.-C. Tseng, C.-T. Huang and L.-G. Chen, “Reconfigurable discrete wavelet transform architecture for advanced multimedia systems,” IEEE Workshop on Signal Processing Systems 2003, pp. 137 – 141, Aug 2003.
[11] M. Ravasi, L. Tenze and M. Mattavelli, “A scalable and programmable architecture for 2-D DWT decoding,” IEEE Transactions on Circuits and Systems for Video Technology, Vol.12, Issue.8 , pp. 671-677, Aug 2002.
[12] K. Andra, C. Chakrabarti, and T. Acharya, “A VLSI architecture for lifting-based forward and inverse wavelet transform,” IEEE Transactions on Signal Processing, Vol. 50, Issue.4 , pp. 966-977, April 2002.
[13] ISO/IEC. ISO/IEC 15444-3. Information technology –Motion JPEG2000. 2002.
[14] ISO/IEC. JTC1/SC29/WG11 Coding of moving pictures and audio. Jan 2001.
[15] A. Cohen, I. Daubechies,and J. Feauveau, “Bi-othogonal bases of compactly supported wavelets,” Comm. Pure Appl. Math., vol. 45, pp. 485-560, 1992.
[16] A. R. Calderbank, I. Daubechies, W. Sweldens, and B.-L. Yeo, “Wavelet transforms that map integers to integers,” Technical report, Deportment of Mathematics, Princeton University, 1996.
[17] M. Grangetto, E. Magli, M. Martina, and G. Olmo, “Optimization and Implementation of the Integer Wavelet Transform for Image Coding,” IEEE Transactions on Signal Processing, Vol. 11, June 2002.
[18] M. Ferretti and D. Rizzo, “Handling borders in systolic architectures for the 1-D discrete wavelet transform for perfect reconstruction,” IEEE Transactions on Signal Processing, Vol. 48, pp. 1365-1378, May 2000.
[19] M. Keating ,Synopsys,Inc and P. Bricaud, Mentor Graphics Cor, “REUSE METHODOLOGY MANUAL --- FOR SYSTEM-ON-A-CHIP DESIGNS (second edition)”, KLUWER ACADEMIC PUBLISHERS, 1999.
[20] R. I. Hartley, “Subexpression Sharing in Filters Using Canonic Signed Digit Multipliers,” IEEE Trans. on Circuit and Systems, Vol. 43, No. 10, pp. 677-688, October 1996.
[21] “nLint® – A HDL Design Rule Checker,” by Novas Softwar, Inc.
[22] JPEG2000 Part5(ISO/IEC 15444-5:2003) Reference Software. http://www.jpeg.org/jpeg2000/j2kpart5.html
[23] K. K. Parhi, University of Minnesota, “VLSI Digital Signal Processing Systems --- Design and Implementation”, A Wiley-Interscience Publication JOHN WILEY & SONS, INC.

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