閥值邏輯是一種布林邏輯表示式，相較於傳統的表示方法具有較精簡的特性。近年來，由於先進奈米材料技術的進步，相關研究紛紛提出有效率的閥值邏輯閘實現方式，因此，閥值邏輯上的研究，如多層合成、驗證及測試，已經被提出來。另一方面，伴隨著各種閥值邏輯閘實現方式，各種延遲模型也被提出，然而在閥值邏輯電路上，卻尚無相關靜態時序分析被提出。由於閥值邏輯，相較於傳統布林邏輯，以一種不同方式來評估功能輸出，因此對於時序關鍵分析上的路徑觸發準則也有所差異。本篇論文提出了第一個針對閥值邏輯閘的路徑觸發準則，並發展在閥值邏輯電路上的靜態時序分析演算法。實驗結果展現該演算法在閥值邏輯電路上，相較於以時序模擬方式，進行時序分析的精確及效能。

Threshold logic has been known as an alternative representation of Boolean logic due to its compactness characteristic. Recently, the developments in advanced nanotechnologies have also promised efficient implementations of threshold logic gates. Thus, many synthesis methodologies for threshold logic circuits have been proposed. On the other hand, the delay models of threshold logic gates accompanied with their implementation development have also been proposed. However, there has not been a timing analysis algorithm for threshold logic circuits to the best of our knowledge. Since threshold logic has a different mechanism in functional evaluation compared to the traditional Boolean logic, a threshold logic gate can represent a more complex function. As a result, the path sensitization criterion for criticality analysis in threshold logic circuits is also different. In this work, we propose a path sensitization criterion for threshold logic circuits, and develop a static timing analysis algorithm. The experimental results show the accuracy and efficiency of the proposed algorithm compared to the dynamic simulation approach for a set of MCNC and IWLS 2005 benchmarks.

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