適用於多記憶體核心系統晶片之改良內含自我測試電路產生器

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研究生：	薛家明 Chia-Ming Hsueh
論文名稱：	適用於多記憶體核心系統晶片之改良內含自我測試電路產生器 An Enhanced Built-In Self-Test Complier for Multiple Memory Cores in System-on-Chip
指導教授：	吳誠文 Cheng-Wen Wu
口試委員:
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2001
畢業學年度：	89
語文別：	英文
論文頁數：	82
中文關鍵詞：	積體電路測試、記憶體測試、自我測試電路、系統晶片測試、測試
外文關鍵詞：	BIST, SOC testing, memory testing, VLSI testing, grouping and scheduling test, diagnosis, BIST compiler, multiple memory and multiple port memory test
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隨著內嵌式記憶體 (embedded memory) 的體積及密度快速成長，內嵌式記憶體在系統晶片 (system on chip, SoC) 內的測試已經成為最重要的一環。為了減少測試的成本及增加易測性，在這篇論文內我們提出了一個針對系統晶片內之內嵌式記憶體自我測試器 (built-in self-test, BIST) 的自動產生架構，稱之為BRAINS2 (Bist for Ram IN Seconds version 2.0)。BRAINS2為我們先前架構BRAINS的改進版，其中加強並解決對單一晶片內含多重記憶體 (multiple memory cores) 及單一記憶體內含多重輸出入埠 (multiple-port memory) 的測試問題。
隨著系統晶片的功能日益強大，記憶體的功能及結構也愈來愈強大及複雜，因而延生出主要三個測試上的問題，1) 記憶體的結構多樣化; 2) BIST的體積過大; 3) 測試的時間過長等。面對種類多而複雜的記憶體我們提供了一個方便使用的BIST自動產生器 (BIST complier or generator) 來幫助使用者在短時間內產生適當的BIST，使用者本身不需具備BIST設計的能力，只須直接輸入記憶體的參數即可，如此可大大的減少設計BIST的時間及成本。由於多重記憶體及多重輸出入埠記憶體的廣泛運用，一般的BIST出現了體積過大及測試時間過長的問題，因此我們提出了一個共用型 (shared) 的BIST架構來減少BIST的面積。然而對於測試時間過長的問題我們使用了分群平行測試 (group test) 的方法來減少測試時間，另外我們更利用一個新的安排技巧 (scheduling technology) 來有效減少測試群組 (test group) 的數目因而更有效的降低測試時間。同時我們將這些方法彙整並基於我們所提出的BIST架構而提出了一個自動分群安排的演算法 (auto-grouping and scheduling algorithm)，來對測試時間及面積做最佳化的設計。

Memory testing is becoming the dominant factor in testing a System-on-Chip (SoC), with the rapidly growth of the size and density of embedded memories. To minimize the test effort, we present an automatic generation framework of memory built-in self-test (BIST) cores for SoC design. The BIST generation framework is a much improved one of our previous works. Test integration of heterogeneous memory architectures and clusters of memories are focused. An automatic test grouping and scheduling algorithm optimize the overhead of memory testing in test time, performance, power consumption, etc. The minimized BIST circuitry can deal with multiple memory cores including various types of multiple-port and single-port SRAMs. With configurable and extensible architecture, the proposed framework facilitates the overall test integration for core providers as well as system integrators among various design and test matrices.

Introduction 1
1 Embedded Memory Testing in SoC  . . . . . . . . . . . . 1

2 Previous Works  . . . . . . . . . . . . . . . . . . . . 2

3 Proposed Approach . . . . . . . . . . . . . . . . . . . 3

4 Organization of this Thesis . . . . . . . . . . . . . . 3

Background 4

1 FaultModels . . . . . . . . . . . . . . . . . . . . . . 4

2 March Algorithms. . . . . . . . . . . . . . . . . . . . 5

BRAINS2 Framework 8

1 Proposed BIST Architecture  . . . . . . . . . . . . . . 9

2 Controller  . . . . . . . . . . . . . . . . . . . . . . 9

2.1 Control State Machine  . . . . . . . . . . . . . . . 12

2.2 Command Storage Chain  . . . . . . . . . . . . . . . 13

3 Sequencer . . . . . . . . . . . . . . . . . . . . . . . 15

3.1 Sequencer Control Module . . . . . . . . . . . . . . 16

3.2 Memory Command Generator . . . . . . . . . . . . . . 17

3.3 Address Generator. . . . . . . . . . . . . . . . . . 18

3.4 TPG Selection Module . . . . . . . . . . . . . . . . 18

3.5 Error Handling Module. . . . . . . . . . . . . . . . 19

4 Test Pattern Generator (TPG). . . . . . . . . . . . . . 20

4.1 CommandConverter . . . . . . . . . . . . . . . . . . 21

4.2 Comparator . . . . . . . . . . . . . . . . . . . . . 21

4.3 Error Handling Module. . . . . . . . . . . . . . . . 21

4.4 Test Collar. . . . . . . . . . . . . . . . . . . . . 21

4.5 Port Selection Module. . . . . . . . . . . . . . . . 22

5 Memory Modeling . . . . . . . . . . . . . . . . . . . . 22

5.1 I/O Modeling . . . . . . . . . . . . . . . . . . . . 24

5.2 Command Modeling . . . . . . . . . . . . . . . . . . 24

5.3 Task Modeling. . . . . . . . . . . . . . . . . . . . 26

5.4 Timing Limitation Modeling . . . . . . . . . . . . . 26

5.5 AC Modeling. . . . . . . . . . . . . . . . . . . . . 29

6 BIST Compilation Flow . . . . . . . . . . . . . . . . . 29

6.1 BIST Intermediate Description (BID) Format . . . . . 32

Features of BRAINS2 37

1 Multiple-Port Memory Test Strategy. . . . . . . . . . . 37

2 Multiple-Memory Cores Test strategy . . . . . . . . . . 39

3 Test Auto-Grouping and Scheduling Algorithm . . . . . . 46

4 Hardware Share Strategy . . . . . . . . . . . . . . . . 59

Experimental Results 61

1 Case Study: 1 . . . . . . . . . . . . . . . . . . . . . 61

2 Case Study: 2 . . . . . . . . . . . . . . . . . . . . . 62

3 Case Study: 3 . . . . . . . . . . . . . . . . . . . . . 66

4 Case Study: 4 . . . . . . . . . . . . . . . . . . . . . 66

5 Case Study: 5 . . . . . . . . . . . . . . . . . . . . . 68

Conclusions and Future Works 70

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