具參數飄移意識動態電壓調整技術之低功耗應用

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研究生：	劉東麟 Liu, Tung-Lin
論文名稱：	具參數飄移意識動態電壓調整技術之低功耗應用 Variation Aware Dynamic Voltage Scaling Techniques for Low Power Applications
指導教授：	馬席彬 Ma, Hsi-Pin
口試委員:
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2009
畢業學年度：	97
語文別：	英文
論文頁數：	71
中文關鍵詞：	低功耗、動態電壓調整、標準元件庫
外文關鍵詞：	Low Power, DVS, Cell Library
相關次數：	點閱：2 下載：0
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隨者半導體製程技術尺寸的縮小，使得近幾十年超大型積體電路(VLSI)的設計在電路的效能及層級上有了很大的改進。然而元件尺寸的縮小，除了會有操作電壓降低和操作頻率增加這些隨著製程演進而產生的好處之外，同時也伴隨了設計可靠度降低的問題。而在近代的數位設計系統中，適應性電壓調變被視為是最有效能夠達到功率節省的設計方法，而且透過這個技術讓系統能動態偵測系統的操作，並給予即時的反應，因此能夠讓設計更加的健全。然而，這種低功耗技術在數位電路的設計階段時比較難以付諸實行。

標準元件流程設計在數位設計上最常被運用在客製化的晶片設計上。而標準元件庫正是這個流程不可或缺的元素之一。因此，在這個前提的假設下，對於標準元件庫的設計，我們提供了一套最佳化元件的流程挑選出具有較低消耗功率的元件尺寸，此元件庫支援操作在標準值以下電壓，另外由於動態電壓調整的考量，我們另外提出了一套後段的實現流程。最後在整個系統中，由於加入了適應性電路的調整，系統便可以順利找出系統電壓的最佳點。另外利用電路中的錯誤偵測電路，我們就能偵測系統在運作時的功能正確性，讓系統更加的完備。

最後，測試電路使用台積電的0.18m的製程進行晶片下線驗證，根據電路之模擬結果，動態電壓調整操作在64-QAM的調變方式下跟原來的保守估計的電壓相比，將會有約50%的功率改善。

With the continuous down scaling of the technology, the performance and levels of CMOS VLSI circuit has been on a tremendous boost over the past decades. However, device scaling, power supply lowering, and frequency increasing of operation that accompany with the technology progress will induce the reliability problem. In modern digital integrated circuit, adaptive voltage scaling is regarded to
be the most efficient way to achieve low power design and which can also make a design more robust. However adopting this low power technique to the digital circuit is difficult in engineering practice at design stage.

In digital system design, cell-based methodology is regarded to be the most popular design flow in the various customized IC design market. Based on this fact, we proposed a simple cell optimization flow to develop a cell library which enables a low voltage operation under nominal value. Meanwhile, voltage scaling technique can be adopted to the modified cell-based design flow. By adding the
adaptive detect circuitry, the voltage value of the system will be adjusted to its optimal point. By the error detection signal report at runtime, we can observe the system correctness and make a more robust design.

Finally, a test circuit is implemented under TSMC 0.18um 1P6M CMOS process. And it shows a dynamic voltage system will have almost 50% power saving comparing to the full margin design.

Abstract i
Introduction 1
1 Backgrounds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2 Motivation of Thesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
3 Contents of Thesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Low Power Design Technique 5
1 Voltage Influence on Power . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Voltage Influence on Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3 Low Power Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1 Multiple Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . 8
3.2 Cluster Voltage Scaling . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.3 Multiple Threshold Voltage . . . . . . . . . . . . . . . . . . . . . . 12
3.4 Adaptive Voltage Scaling . . . . . . . . . . . . . . . . . . . . . . . . 14
Self-Aware Adaptive Power Control System 17
1 Timing Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2 Voltage Margin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3 Double Sampling Technique . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4 Timing Error Tolerant Design . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5 Dynamic Voltage Scaling System . . . . . . . . . . . . . . . . . . . . . . . . 27
Modified Cell-Based Design flow 29
1 Standard Cell Library Development . . . . . . . . . . . . . . . . . . . . . . 29
2 Cell Design and Optimization Flow . . . . . . . . . . . . . . . . . . . . . . 31
3 Characterization Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4 Characterization Table Decision . . . . . . . . . . . . . . . . . . . . . . . . 33
5 Characterization Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.1 Input Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.2 Maximum Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.3 Propagation Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.4 Transition Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.5 Setup Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5.6 Hold Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5.7 Recovery Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5.8 Removal Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5.9 Minimum Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . . 39
6 Routing Grid Decision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
6.1 Routing Grid Width . . . . . . . . . . . . . . . . . . . . . . . . . . 40
7 Cell Physical View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
8 Low Voltage Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
8.1 Low Voltage Library Creation . . . . . . . . . . . . . . . . . . . . . 45
9 Special Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
9.1 Clock Gating Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
9.2 Level Shifter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Test Chip Implementation and Measurement Results 51
1 Test Circuit : Sphere Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . 51
2 Circuit Block Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3 Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
3.1 I/O Decision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
3.2 Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
3.3 Auto Placement and Route . . . . . . . . . . . . . . . . . . . . . . . 55
3.4 Design for Testability . . . . . . . . . . . . . . . . . . . . . . . . . . 56
4 Simulation Result: Analysis and Discussion . . . . . . . . . . . . . . . . . . 58
4.1 Simulation Result . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
4.2 Comparison Table . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
4.3 DVS Application for Sphere Decoder . . . . . . . . . . . . . . . . . 59
4.4 Error Recovery Mechanism . . . . . . . . . . . . . . . . . . . . . . 60
Conclusion 67
1 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
2 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

                                

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