電子鼻的發展已有一段長遠的歷史，但大部分電子鼻體積可觀；且目前在電子鼻後端的辨識系統中，大部分是將訊號以軟體分析或微處理器等方式進行運算，相當耗能；另外，介面電路取得的類比訊號需經過類比數位轉換器將訊號轉換成數位訊號才能讓軟體或微處理器運算，也消耗了多餘的功率。因此用類比電路製作倒傳遞多層感知器類神經網路，以此電路作為電子鼻系統的辨識與分類工具；透過晶片整合縮小體積，並直接以類比電路運算降低功率需求，實現適於可攜式電子鼻系統的類比倒傳遞多層感知器類神經網路，將可大幅開拓電子鼻的應用發展領域。
本研究以三種不同的氣味作為多層感知器類神經網路的學習目標，採用4-4-1的網路結構，即輸入層與隱藏層各包含四個神經元，輸出層僅用一個神經元；一般輸出層神經元數目取決於目標輸出值的個數，然而就降低功率消耗以及縮小面積的電路設計觀點來說，越多的神經元意味著需要用更多的突觸連接不同層之間的神經元；因此在輸出層僅用一個神經元做為網路輸出層的運算單元，以不同的數值作為不同的輸出目標值，藉以縮小電路面積與功率消耗。然而以電路實現此結構卻會受限於狹窄的輸出變動範圍，所以在輸出層神經元之後加入兩個比較器，藉比較器的輸出結果判斷氣味種類。電路上大量採用操作於次臨界區區並達到飽和的電晶體，其電壓-電流為指數關係的概念進行設計，包含乘法器、活化函數與其近似微分等。活化函數以輸入端電晶體操作於次臨界區並達到飽和的基本差動對，產生具有雙曲正切函數特性的輸出；而其微分則利用導函數定義以及函式的自變數-應變數觀念，設計一個只需另加一組基本差動對與一組電流鏡結合活化函數電路，實現活化函數與其近似微分之電路。
本研究以TSMC 0.18 μm 1P6M CMOS製程實現倒傳遞多層感知器類神經網路的類比電路，晶片模擬與量測結果顯示網路經過訓練後具學習、容錯與辨識能力，其辨識率可達98.33%。晶片面積只有1.353 × 1.353 mm2且功率消耗僅0.423 mW，應用於可攜式裝置是項優勢。

This thesis presents an analog multilayer perceptron (MLP) neural network circuit with on-chip back propagation learning. This low power and small area network was proposed to implement as a classifier, which is intended to be used in a portable electronic nose (E-nose).
The proposed MLP architecture was composed of four signal inputs, four hidden neurons (HN), one output neuron (ON). Twenty hidden synapses (HS) and five output synapses (OS) were used to connect neurons between different layers. Two comparators were utilized to clarify further the classification results. This simple structure allowed the circuit to have a smaller area and less power consumption. Both HS and OS were basically composed of two multipliers (Chible multiplier, CM. and Gilbert multiplier, GM), one weight unit W, and a back propagation multiplier (BPM) in OS was required to generate the back propagated error term. The Chible multiplier was chosen for CM and BPM because of its favorable linearity and wide operation range related to weights. A backward multiplier GM was adopted from the Gilbert multiplier to generate weight adaption value. The weight unit was a temporal signal storage device exhibiting the adaptation of weight value, and was implemented by MOSCap because of its smaller area. HN and ON consisted of an activation function circuit, its approximate derivative circuit, and a Delta block that calculated the error terms. The realization of the activation function simply involved a differential pair with input transistors operating in weak inversion and saturation region. The approximately derivative of the activation function was realized by implementing another differential pair with the referenced input node slightly different from that of the original one.
To test the analog MLP, six hundred odor samples of three kinds of fruits were used. Three hundred samples were used to train the system; the MLP system learned to follow the target output successfully during the training procedure. After training, the other three hundred fruit odor samples were fed into the system to perform classification.
The circuit was fabricated using TSMC 0.18 μm 1P6M CMOS process with 1.8 V supply voltage. The area of this chip was 1.353 □ 1.353 mm2 and the power consumption was 0.423 mW. Chip measurements showed that the proposed analog MLP circuit could be successively trained to identify three fruit odors with 98.33% accuracy.

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