隨著可攜式電子產品的發展朝向省電、多功能整合發展，加上電晶體尺寸隨著摩爾定律不斷微縮，晶圓的生產成本也不斷提高而且製程微縮到奈米維度時遇到許多瓶頸，所以利用矽穿孔進行三維晶片堆疊整合的三維積體電路成了時下最熱門的研究題目。不過三維積體電路的技術尚未成熟，良率低與高成本是三維積體電路無法量產之原因。因此，較低成本且易實作的2.5D中介層整合的架構被提出，2.5D中介層整合系統利用中介層上面的重分佈層提供通道給晶片與晶片之間互相溝通。但是當晶片整合至中介層上後沒有辦法進行測試整體的效能與晶片與晶片之間的連線是否有開路或短路，更無法進一步得出系統的效能極限為何。
我們提出一應用於2.5D中介層整合系統的時序特性萃取方法，此方法利用晶片內部的發送器與接收器再加上用來協助分辨資料的處理功能塊，並利用量測手法來完成各個區塊的時序特性萃取。

With the development of mobile device towards low-power design and multi-function design. Also, transistor size is shrinking continuously based on Moore’s Law, the cost and difficulties of chip fabrication are getting higher and higher. Duo to these demands and problems, 3D Integration Chip (3D IC) by using TSV (Through Silicon Via) technology become the most popular research topic. However, the technology of 3D IC hasn’t fully developed yet. Lower yield and high cost are the bottleneck of mass production. Therefore, 2.5D Interposer Integrate System IC is proposed which has advantages like low cost and fabrication easily. Chips on 2.5D Interposer Integrate System communicate with each other by redistribution layer. But when chip once mounted on interposer, we can’t test whole system performance and whether the redistribution layer is open or short.
We proposed a timing characteristic extraction methodology for 2.5D interposer integrate system. Using the transceiver and receiver circuit inside chip and data processing circuit to extract the timing characteristic of each block.

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