快閃式非揮發可程式抹除記憶體已廣泛地應用在可攜式電子產品，諸如數位相機、手機、數位播音機。快閃記憶體隨著應用層面的擴大，市場供不應求。 記憶體產品定位在提供高速編碼及高密度快閃記憶體。本文之第一部份提出在新動態頁暫存架構下的『新最高效能多頁並行編碼技術』，靜態頁暫存器以新的動態頁暫存器取代，以達成最高速編碼的優越特性，該技術之各種關鍵分散式局部暫存元件設計為本文討論的重點。『新最高效能多頁並行編碼技術』可同時處理多頁編碼，免除靜態頁暫存器有限容量所導致編碼速度無法提升的窘境。因此，分散式局部暫存技術(即嵌入動態存取記憶體於快閃記憶陣列之中)，取代陣列外暫存器的角色，降低資料停留在陣列外暫存器的時間，進而提升資料寫入速度。 依快閃記憶體陣列結構分類，本文提出：(a) NAND動態記憶胞局部暫存、(b) DINOR動態位元局部暫存、(c) AND動態區段局部暫存和增強位元式動態區段局部暫存，以及電容板增強位元式區段局部暫存等新關鍵元件技術。局部暫存元件之設計影響快閃記憶體編碼特性，必須遵循新的設計原則才能有效率的編碼，同時，配合新的兩段式偵測恢復法，編碼中的臨界電壓可被有效的控制，暫存信號也可藉此恢復。本文所提技術針對大量資料湧入特別有效，是未來不可或缺的高速編碼技術。
本文第二部分討論多值邏輯儲存技術，多值邏輯儲存可有效增加容量及降低單位成本，不過如何精準地控制存放電荷量卻考驗控制線路的設計。本文提出用於N型通道記憶體的『新源極控制自我校正法』及用於P型通道記憶體的『新自我調整動態源極法』來達成多值邏輯儲存。新技術可因準確地控制儲存電荷以提升記憶體整體的耐久度，降低編碼功率消耗，減緩干擾效應，是未來可攜式低功率需求應用中不可或缺的多值編碼技術。

Flash EEPROM has been widely used in mobile applications, such as digital camera, cellular phones and music players. The market is rapidly growing along with the new application fields. The major developing trends include fast writing throughput and high-density storage. In the first part of this dissertation, a novel power limited multiple page parallel programming (MPP) technique in the new dynamic buffer architecture is proposed for enhanced programming. The novel power limited MPP utilizes dynamic buffers for continuous loading of programming data and employs dynamic local latching for storing signals. This innovation overcomes the conventional writing-speed limitation of static buffers. The proposed local latching techniques include (a) NAND Dynamic Cell Latching (DCL), (b) DINOR Dynamic Bit-Line Latching (DBL), (c) AND Dynamic Sector Latching (DSL), Boosting Bitline Dynamic Sector Latching (BB-DSL), and Capacitor-Plate Boosting Bitline Dynamic Sector Latching (CBB-DSL). We found that latching devices strongly affect the programming characteristics of Flash memory. A novel two-step sense and refresh algorithm is proposed to control threshold voltages in the dynamic buffer architecture. This algorithm features reduced dynamic buffer sizes, enhanced programming, and capability of controlling threshold voltages. The new approach greatly improves the programming throughput, which is very suitable for future high-speed Flash memory applications.
The second part of this dissertation discusses two novel multi-level programming techniques, the Source-Controlled Self-Verified (SCSV) method for N-channel EEPROM and the Self-Adjusted Dynamic Source (SADS) method for P-channel Flash memory. The SCSV method achieves nondegraded multilevels in the proposed high-impedance loaded configuration, extending endurance cycles by the self-verified mechanism. The SADS method introduces a multilevel P-channel hot carrier programming with the new drain-controlled source voltage in the newly developed constant current driven source configuration. Fast and low power multilevel programming is successfully achieved. The two techniques provide promising solutions for future reliable high-density applications.

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