多重臨界電壓互補金屬氧化物導體是解決漏電流一個很有效的技術。而設計時，靜態電晶體的大小是最重要且關鍵的因素。如果此電晶體的面積太大，電路的效率可以維持但所耗的動態能量就能增加。相反的，如果電晶體的面積太小，電路的效能就會受很大的影響。有些研究提出以彼此間完全互斥的放電模式來設計靜態電晶體的大小。但是一般的研究都只有考慮到電路的拓蹼資訊。我們發現以邏輯功能為導向來說，二個有可能同時發生轉變的邏輯閘並不一定會同時放電。因此，我們提出一個演算法流程同時考慮了包括拓蹼資訊與邏輯功能的資訊來完成叢集邏輯閘的方法，叢集的邏輯閘可以共用一個靜態電晶體來節省面積的消耗。我們的實驗結果顯示我們的方法在考慮邏輯功能下對於靜態電晶體的個數可以節省百分之18左右的程度也證明我們的方法可以有效的達到在設計多重臨界電壓互補金屬氧化物導體時所需考慮的問題。

Multi-Threshold CMOS (MTCMOS) is a circuit style that can effectively reduce leakage power consumption.
Sleep transistor sizing is the key issue when MTCMOS circuit is designed.
If the sleep transistor size is too large, the circuit performance can be maintained but the dynamic power consumption of the sleep transistor will increase.
On the other hand, if the sleep transistor size is too small, there will be significant performance degradation because of the increased resistance to ground.
Previous approach designed the sleep transistor size based on mutual exclusive discharge patterns.
However, these approaches considered only topology of a circuit.
We observed that two possible simultaneous switching gates may not discharge at the same time in terms of functionality.
Thus, we propose an algorithm to determine how to cluster cells to share sleep transistors taking both topology and functionality into consideration.
The results show that the proposed method can achieve on the average 18% reduction ratio in terms of the number of sleep transistors as compared to the method without considering functionality.

[1]“BSIM3 Homepage.” http://www-device.eecs.berkeley.edu$\sim$bsim3/arch\_ftp.html.

[2]　Shekhar Borkar,
"Low Power Challenges for the Decade",
Proceedings of ASP-DAC, pp. 293-296, 2001.

[3]　Dongwoo Lee and David Blaauw,
"Static Leakage Reduction through Simultaneous Threshold Voltage and State Assignment,"
Proceedings of the 40th conference on Design automation, pp. 191-194, 2003.

[4]　Rahul M. Rao, Frank Liu, Jeffrey L. Burns, and Richard B. Brown,
"A Heuristic to Determine Low Leakage Sleep State Vectors for CMOS Combinational Circuits,"
Proceedings of ICCAD, pp. 689-692, 2003.

[5]　Dongwoo Lee, Harmander Deogun, David Blaauw, and Dennis Sylvester,
"Simultaneous State, Vt and Tox Assignment for Total Standby Power Minimization,"
Proceedings of DATE, pp. 494-499, 2004.

[6]　Yen-Te Ho, TingTing Hwang,
"Low Power Design Using Dual Threshold Voltage,"
Proceedings of ASP-DAC, pp. 205-208, 2004.

[7]　S.Muth, T.Douseki, T.Matsuya, T.Aoki, S.Shigematsu, and J.Yamada,
"1-V Power Supply High-Speed Digital Circuit Technology with Multithreshold-Voltage CMOS,"
IEEE Journal of Solid-State Circuits, vol. 30, no. 8, pp. 847-853, Feb. 1995.

[8]　J.Kao, A.Chandrakasan, and D.Antoniadis,
"Transistor Sizing Issues and Tool for Multi-threshold CMOS Technology,"
Proceedings of the 34th conference on Design automation, pp. 409-414, 1997.

[9]　J.Kao, S.Narendra, and A.Chandrakasan,
"MTCMOS Hierarchical Sizing Based on Mutual Exclusive Discharge Patterns,"
Proceedings of the 35th conference on Design automation, pp. 495-500, 1998.

[10]　Mohab Anis, Shawki Areibi, Mohamed Mahmoud, and Mohamed Elmasry,
"Dynamic and Leakage Power Reduction in MTCMOS Circuits Using an Automated Efficient Gate Clustering Technique,"
Proceedings of the 39th conference on Design automation, pp. 480-485, 2002.

[11]　Harish Kriplani, Farid N. Najm, Ibrahim N. Hajj,
"Pattern Independent Maximum Current Estimation in Power and Ground Buses of CMOS VLSI Circuits: Algorithms, Signal Correlations, and Their Resolution,"
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp. 998-1012, 1995

[12]　Sablh H. Gerez,
"Algorithms for VLSI Design Automation," pp. 265-267.