隨著半導體製程技術的演進，越來越多的電路可以整合到同一顆晶片裡面，電路的功能性跟複雜度迅速的提升，伴隨而來的是測試的困難度以及測試成本隨之成長，根據國際半導體技術報告（ITRS’03）指出，測試成本是唯一一個不會隨半導體技術演進而降低的成本。另外，近幾年也有人提出無線測試的想法，目的是要改善傳統測試所造成的一些非理想狀況，包含改善因為接觸式測量所造成的誤差以及提高提高對待測電路的存取度（accessibility）。
在本篇論文裡，我們提出了一個無線測試系統的架構，並結合了可測試性設計（Design-For-Testability-DFT）的概念。紅外線發射元件（IrDA transceivers）用來實現無線通訊的介面，同時我們也建構了一個圖形化使用者操作介面（GUI）的測試軟體來驗證及展示本無線測試系統。在測試系統理我們將會展示兩種可測試性設計，包含內建式自我測試(Built-in Self Test-BIST)技術以及掃瞄鏈（Scan Chain）設計。為了驗證內建自我測試技術，我們會實做記憶體內建自我測試技術，FPGA內部的記憶體將會當成我們待測的記憶體。而內建自我測試電路將由自我測試電路編譯器（BIST compiler）產生。另一方面，我們會將一個簡單的序相邏輯電路ISCAS’89 -S27當成我們掃瞄模式的待測核心（Core Under Test），而待測核心將會先經過Design Compiler嵌入掃瞄鏈。
在待測電路端，微型控制器AT89C51將會實做為測試控制器，它除了接收從紅外線收發器所傳送過來的串列資料外，並且判斷從測試機台所送過來的指令，決定要做什麼樣的測試模式，送出所相對應的控制訊號及測試資料。當整個測試流程完成之後，它將負責將測試的結果送回給測試機台端，測試機台將判斷從待測電路回傳回來的資料，並顯示測試的結果。

Abstract

Test cost and test accuracy are very important issues in novel circuit designs. According to the ITRS’03 report, test cost will never decrease with the advancement of integrate circuit fabrication technology. Focused on the test challenges, wireless test concepts are presented in recent years, since these approaches remove many dependencies found in traditional wire test structures and promote the accessibility of cores.
In this thesis, a prototype with DFT designs is proposed to verify the overall concept of this wireless test system. To implement the wireless test system, the IrDA transceivers are applied as our wireless communication interface, and a micro-controller is applied as the test controller in our system. To demonstrate this system, a graphical user interface program is also constructed. Two types of DFT techniques including Build-In Self-Test and scan are implementation in this system. To verify the BIST operation, a 512K-Byte FPGA internal block RAM is taken as memory under test and the MBIST circuit is generated by BIST compiler. On the other hand, a simple ISCAS89 benchmark circuit S27 that has embedded scan chain inside through Design Compiler is applied to demonstrate the scan operation.

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