研究生: |
蔡昀廷 Tsai, Yun-Ting |
---|---|
論文名稱: |
標準CMOS製程中橫向NPN電晶體於高動態範圍影像偵測器之應用 Application of the Lateral NPN Transistor in 0.18 μm Standard CMOS Technology to High Dynamic Range Image Sensor |
指導教授: |
徐永珍
Hsu, Klaus Yung-Jane |
口試委員: |
江雨龍
Jiang, Yue-Long 賴宇紳 Lai, Yu-Sheng |
學位類別: |
碩士 Master |
系所名稱: |
電機資訊學院 - 電子工程研究所 Institute of Electronics Engineering |
論文出版年: | 2021 |
畢業學年度: | 109 |
語文別: | 中文 |
論文頁數: | 72 |
中文關鍵詞: | 標準製程 、影像感測器 、橫向式電晶體 、高響應度 、高動態範圍 、光偵測器 |
外文關鍵詞: | standard cmos technology, image sensor, lateral phototransistor, high dynamic range, high responsivity, photodetector |
相關次數: | 點閱:2 下載:0 |
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近年來隨著科技的日新月異,影像感測器在人們的生活扮演了舉足輕重的角色。目前市面上的影像感測器在低光源與高動態範圍下的影像處理大多仰賴後續的軟體整合,而本研究之目的是在不更動任何現有製程條件下,以TSMC標準製程製作出具有高響應度的橫向式光電晶體作為影像感測器像素中的感光元件,並搭配本論文之高動態範圍之像素陣列、結合二次相關取樣電路以消除雜訊與暗訊號,且將數位訊號之生成電路與偏壓電路整合於一片晶片之中。
本研究使用標準的TSMC 0.18 μm 1P6M Standard CMOS製程做整合,實際下線晶片影像陣列為64×48陣列。利用純矽製程製作出高響應度之橫向式光電晶體嘗試實踐一個具有高動態偵測範圍之影像感測系統,相較於過去實驗室所實踐之建構於Bi-CMOS製程下的晶片系統,本研究具有較低的成本,對於可商品化來說是一大優勢。
晶片本身並未封裝,面積包含Pads為3.305 mm2,外接專門設計之PCB板進行量測。量測結果發現,由於佈局時並未妥善考量走線上數位訊號與類比訊號之間過於靠近或交錯會造成輸入基頻訊號對類比輸出訊號產生干擾。本次電路應用確實能在輸入基頻的控制下依序將訊號傳出,但受限於佈局疏失無法有效實現橫向式電晶體在影像感測器上的表現。
Recently, image sensors played a decisive role in human’s life as technology has had a rapid progress. Currently, most image sensors on the market rely on rear end image processing by software engineering when dealing with low light and high-contrast images. In this thesis, my goal is to make a lateral phototransistor (LPT) with high responsivity and use it as the photodetector in the image sensing array without any process modifications. The high dynamic range 64×48 pixel array with the embedded LPT’s was integrated with a digital circuit, a bias circuit, and a correlated double sampling circuit which is designed to eliminate fixed-pattern noise and dark signals.
The image sensor with a 64×48 pixel array was fabricated with the TSMC 0.18 μm 1P6M Standard CMOS technology. Using the pure CMOS technology to implement a high dynamic range image sensing system has an obvious cost advantage for commercialization when compared with using the 0.18 μm Standard SiGe BiCMOS technology adopted by our laboratory previously.
The area of the sample chip is 3.305 mm2 and it is not packaged. A specific PCB board was designed to finish the measurements. According to the measurement, input clock signal produces interferences to the output signal due to my lack of consideration during layout. The metal lines of digital signals and analog signals, which are too close or cross each other, would cause bad influence to the chip. In this design, we indeed observed the sequential output signal under the control of input clock and digital circuit. Nevertheless, the performance of lateral phototransistors on image sensors could not be observed effectively due to the interferences.
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