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研究生: 應允皓
Yun-Hao Ying
論文名稱: 一低功率測試壓縮方法-低功率萬用多重傳送掃描
A Low Power Test Compression Scheme- Cool Universal Multi-Casting Scan(CUMC-Scan)
指導教授: 黃錫瑜
Shi-Yu Huang
口試委員:
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年: 2007
畢業學年度: 96
語文別: 英文
論文頁數: 38
中文關鍵詞: 低功率
外文關鍵詞: Test Compression, CUMC, Low Power
相關次數: 點閱:2下載:0
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  • 在本篇論文中我們提出了一個測試架構-低功率萬用多重傳送掃描,在此架構之架構之下,我們不僅針對功率消耗做了一些改進,對於傳遞資料部分(shift)以及擷取資料部分(capture),我們都提出了方法來作改進,藉此降低功率消耗上的問題,在此架構之下,我們也兼具了其他功能,例如:減少測試所需的時間以及資料量。在兼顧到測試壓縮(test compression)的方法之下,針對傳送資料(shift)以及擷取資料(capture)我們各別提出了:萬用分段傳送(universal segmented shift)以及依據多重測試之部分擷取(multi-testing based partial capture),透過此兩種方法可以幫助我們有效的解決功率消耗的問題。另外,在我們的架構之下,並不需要特殊的自動產生測試資料的程式(ATPG),也不需要去對於掃描架構部分做額外修改。最後在實驗部份,使用了真實的設計電路當作我們使用的測試對象,透過數據的呈現,也證實了我們在平均以及瞬時功率消耗下都可以達到不錯的節省效果,並且我們更加兼顧到測試壓縮的優勢。透過本篇論文所提出的架構,不僅在解決功率消耗的問題下得到了一個解決辦法,也可以兼顧到在測試壓縮的成本。


    We present a scan test methodology – called Cool Universal Multicasting Scan (CUMC-Scan) for not only compressing test data volume but also reducing scan test power. Combining the universal segmented shifting and multi-testing based partial capture, it is the first time to solve the overall scan test power violation under a test compression scheme. CUMC-Scan doesn’t need any support from specific ATPG tool and modification on the existing scan architecture. The experimental results indicate we can reduce 88.6% average power and 34.7% peak power in average for real designs.

    Contents Abstract…………………………………………………….……………1 Contents………………………………………………..………...………2 List of Figures…………………………………………………….……..4 List of Tables………………………………………………………….....5 Chapter 1 Introduction…………………………………………………6 Chapter 2 Previous Works…………………..………………..……..….8 2.1 Previous Works on Low Power Techniques………….….…….8 2.2 Previous Works on Low Power Test Compression….….…….10 Chapter 3 Cool Universal Multicasting Scan .………..…………..….11 3.1 CUMC-Scan Methodology………..…...……………….…….11 Chapter 4 Power Cooling Techniques……..……..………………..….16 4.1 Fan-Out Driven Grouping……………………………...…….16 4.2 Universal Segmented Shifting………………………….…….18 4.3 Multi-Test Based Partial Capture………...…………….…….19 4.4 Multiple Modes of CUMC-Scan……………………….…….21 Chapter 5 The Architecture of CUMC-Scan……………………..….24 5.1 The Detailed CUMC Controller……………………….…….24 5.2 The Gate Count Profiling of CUMC Controller……….…….26 Chapter 6 Experimental Results…….……..…….………………..….27 6.1 The Overall Flow of CUMC-Scan…………..………….…….27 6.2 The CUMC-Scan Experimental Results……………….…….29 6.2.1 The Results of Power Reduction and Test Compression.30 6.2.2 UMC-Scan vs. CUMC-Scan…………………………...31 6.2.3 Comparison Results with Different X-Filling Methods..33 Chapter 7 Conclusion………….……..……………………..……..….35 Bibliography……………………………………...……………………36

    [1] P. Girard, “Low Power Testing of VLSI Circuits: Problems and Solutions”, Proc. of Int’l Symp. On Quality Electronic Design (ISQED’00), pp. 173-179, 2000.

    [2] J. Saxena, K. M. butler, V. B. Jayaram, S. Kundu, N. V. Arvind, P. Sreeprakash, and M. Hachinger, “A Case Study of IR-drop in Structured At-Speed Testing”, Proc. of Int’l Test Conf. (ITC’03), pp. 1098-1104, 2003.

    [3] C.-W. Tzeng, and S.-Y. Huang, “UMC-Scan Test Methodology – Approaching the Maximum Test Compression of Multicasting”, VLSI Test Technology Workshop (VTTW’07), July 2007.

    [4] R. Sankaralingam, and N. A. Touba, “Controlling Peak Power During Scan Testing,” Proc. of VLSI Test Symp. (VTS’02), pp. 153-159, 2002.

    [5] W. Li, S.M. Reddy, and I. Pomeranz, “On Reducing Peak current and Power During Test,” Proc. of the IEEE Computer Society Annual Symp. on VLSI (ISVLSI’05), pp. 156-161, 2005.

    [6] S. Remersaro, L. Lin, Z. Zhang, S.M. Reddy, I. Pomeranz, and J. Rajski, “Preferred Fill: A Scalable Method to Reduce Capture Power for Scan Based Designs,” Proc. of Int’l Test Conf. (ITC’06), pp. 1098-1104, 2006.

    [7] J. Sazena, K. M. Butler, and L. Whetesel, “An Analysis of Power Reduction Techniqeues in Scan Testing”, Proc. of Int’l Test Conf. (ITC’01), pp. 670-677, 2001.

    [8] K.-J. Lee, T.-C. Huang, and J.-J Chen, “Peak-Power Reduction for Multiple-Scan Circuits During Test Application,” Proc. of Asian Test Symp. (ATS’00), pp. 453-458, 2000.

    [9] P. Rosinger, B. M. Al-Hashimi, and N. Nicolici, “Scan Architecture with Mutually Exclusive Scan Segment Activation for Shift- and Capture-Power Reduction”, IEEE Trans. On CAD of Integrated Circuits and Systems (TCAD’04), vol. 23, no. 7, pp. 1142-1153, July 2004.

    [10] K.-J. Lee, S.-J. Hsu, and C.-M. Ho, “Test Power Reduction with Multiple Capture Orders,” Proc. of Asian Test Symp. (ATS’04), pp. 26-31, 2004.

    [11] A. Chandra, K. Chakrabarty, “Low-Power Scan Testing and Test Data Compression for System-on-a-Chip”, IEEE Trans. On CAD of Integrated Circuits and Systems (TCAD’02), vol. 21, no. 5, pp. 597-604, May 2002.

    [12] R. Sankaralingam, R. R. Oruganti, and N. A. Touba, “Static Compaction Technique to Control Scan Vector Power Dissipation,” Proc. of VLSI Test Symp. (VTS’00), pp. 35-40, 2000.

    [13] A. Al-Yamani, Erik Chmelar, and M. Grinchuck, “Segmented Addressable Scan Architecture”, Proc. of VLSI Test Symp. (VTS’05), pp. 405-411, May 2005.

    [14] Lin, C.-L Lee, J.-E. Chen, K.-L. Luo, and W.-C. Wu, “A Multiplayer Data Copy Test Data Compression Scheme for Reducing Shifting-in Power for Multiple Scan Design”, IEEE Trans. on Very Large Scale Integration (VLSI) System, vol. 15, no. 7, July 2007.

    [15] G. Mrugalski, J. Rajski, D. Czysz, and J. Tyszer, “New Test Data Decompressor for Low Power Applications,” Proc. of IEEE/ACM Design Automation Conf. (DAC’07), pp. 539-544, June. 2007.

    [16] J. Rajski, J. Tyszer, M. Kassab, and N. Mukherje, "Embedded Deterministic Test,” IEEE Trans. on Computer-Aided Design, vol. 23, no. 5, pp. 776-792, 2004.

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