隨著低功耗已經成為晶片設計上考量的重要因素之一，有許多低功耗的設備裝置被許多人提出並且探討其中的課題，在眾多低功耗的設備之下，由於單電子電晶體(Single-Electron Transistor)在室溫下的操作過程中的低功耗，這項裝置受到了相當大的關注。時至今日，近期有針對單電子電晶體架構的自動化合成方法被提出以便於設計上的實現。這項自動化合成方法首先利用二元決策圖(Binary Decision Diagram)來計算出設計功能中的乘積項，接著調整這些乘積項合成之順序來最小化單電子電晶體的架構。透過觀察可知乘積項的個數會對合成出來的單電子電晶體的架構產生莫大的影響，有鑒於此，在這篇論文我們提出了線性臨界值邏輯電路(Linear Threshold Logic Circuit)的乘積項演算法並將此演算法整合到之前提出的自動化合成方法來最小化合成後的單電子電晶體之架構。從實驗結果中顯示，相比於目前最新的單電子電晶體自動化合成方法，我們所提出的方法可以大約節省下１４％的面積以及１６％的寬度。

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