隨著單系統晶片的風行，靜態隨機存取記憶體扮演著越來越重要的角色。近年來，由於內嵌式記憶體的大量使用，使得不管是學界還是業界，都注重在高速或是低功耗的靜態隨機存取記憶體的設計上；讓我們仔細思考一個問題，當我們都只專注在電路設計，卻忽略了我們的設計是不是可以有高良率的產出，將會使我們做出來的晶片大部分變成是浪費資源的垃圾。尤其在現今的晶片設計上，我們可以發現有超過百分之五十以上的面積，都是讓靜態隨機存取記憶體給佔去；也就是說，靜態隨機存取記憶體在晶片中有較高的比例會發生損毀的情形，所以如何在設計的時候，就考量晶圓製程變異所造成的靜態隨機存取記憶體損毀的問題，是我們的首要課題。在此，我們提出了分割攻破的方法，來做靜態隨機存取記憶體的良率分析。主要的目標是希望在不喪失良率分析精準度的情況下，加快我們的分析速度。為了達到這樣的目標，我們使用了兩個主要的技巧；首先，我們藉由模擬軟體，建立一個控制電路的輸出波型的模型。接著，我們使用這些模型來重建一組輸入波，讓8×8 的靜態隨機存取記憶體陣列來使用。藉由這些輸入的訊號和軟體的模擬，我們可以在記憶體陣列的輸出端，得到一些邏輯1或是邏輯0的值，來判斷陣列內的記憶體單元，是否是正常運作，最後我們就可以得到良率的預估值。實驗的結果顯示，我們的方法可以比傳統模擬靜態隨機存取記憶體快上三百倍的模擬時間，而且和它相比卻僅僅只有百分之三的誤差；由此可見，我們的方法是有效率又精確。

We present a divide-and-conquer methodology for SRAM yield analysis. The ultimate goal is to accelerate the speed of yield analysis without missing accuracy. There are two major techniques in this methodology. Firstly, we attempt to establish the model of control circuit output signal through HSPICE simulation. Secondly, we use the model from first step to re-generate input pattern waveforms for 8×8 SRAM array. Then, take these waveforms into 8×8 SRAM array HSPICE file and run simulation. Finally, we can get a yield prediction value. Experimental results shows that this two-level abstraction method can speed up the yield estimation process by 300 times, whereas keeping the estimation error to only 3% as compared to the traditional time-consuming simulation with the entire SRAM circuit.

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