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研究生: 黃嘉常
論文名稱: 考量等候時間限制之半導體製造在製品分配及控制方法
WIP Allocation and Control Considering Time Constraint in a Semiconductor Manufacturing System
指導教授: 劉志明
口試委員:
學位類別: 碩士
Master
系所名稱: 工學院 - 工業工程與工程管理學系
Department of Industrial Engineering and Engineering Management
論文出版年: 2007
畢業學年度: 95
語文別: 中文
論文頁數: 99
中文關鍵詞: 在製品存貨量在製品分配與控制等候時間限制等候理論類神經網路
外文關鍵詞: WIP level, WIP control, queueing theory, neural network, time constraint
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  • 半導體產業在競爭的環境之下,如何提高生產量,並藉由降低在製品水準來降低生產週期時間為首要課題。而半導體製造當中存在著再回流特性與複雜的製程,使得在製品存貨量的管理變得相當困難。在管理者無法掌控在製品存貨量的情況下,會造成產出量不穩定,生產週期時間更加不易掌控,週期時間的變異也跟著上升,因此,本研究提出了一套在製品存貨的控制方法,利用倒傳遞類神經網路(Back Propagation Neural Networks;BPNN)來釐清產出、生產週期時間、在製品水準這三者的關係,並且訂下整廠與瓶頸工作站最適的在製品水準。
    此外,在考量某些上下游站別之間存在的等候時間限制,本研究利用倒傳遞類神經網路找出等候限制時間的長短與在製品數量的關係,以決定出該站別的在製品水準上限,以避免在製品數量過多導致等候時間超過等候時間的限制,有效降低因超過等候時間限制而重工的機率;沒有等候時間限制的站別則先透過過去歷史資料的分析整理,找出上游機台批量大小與下游機台的來到間隔時間變異係數(Ca)的關係,並將此Ca值代入等候線理論中的GI/G/m模型來決定其該分配到的在製品數量為多少。最後,以參考文獻當中所提出的最小存貨變異派工法則(MIVS)為基礎,並針對此派工法則如未考量多種產品組合、以及將在同一個生產優序內的每個晶圓批的重要性視為相同等缺點,利用X-Factor來作為第二層次的派工優序判斷標準,使得原先所定下的每個工作站的標準在製品水準得以藉由此修正後的MIVS派工法來加以維護。透過此新在製品標準,再加上兩層次的派工判斷,使平均生產週期時間降低了約11%,生產週期時間的變異則下降了約13%,此外,因超過等候時間限制而重工的機率也能夠有效下降。


    In order to meet the requirement of short product life cycle, the goal of most semiconductor manufacturing is to reduce its manufacturing cycle time and to deliver products at the right time. Base on Little’s Law, cycle time is proportional to the WIP level, given the same throughput rate. Therefore, in order to reduce the cycle time, the most important thing is to control the WIP. From the Theory of Constraints (TOC) , the throughput of a bottleneck workstation is the determinant of the entire fab throughput ,so the first step to control the WIP is to set reasonable WIP levels for the bottleneck workstation and the entire Fab, In this study, the bottleneck WIP and the total fab WIP are estimated by using the neural networks, and then the remaining WIP are allocated to other operations .
    In addition, because of yield consideration, a queue time limit is usually set between two continuous operations, which are called the queue time constraint. If the queue time of a lot exceeds the queue time constraint, the lot will be send back to the previous operation for rework .If the times of rework are too many, a lot may even be discarded. So, before allocating the WIP to each operation, setting a reasonable WIP level for the operations which contain the queue time limit to prevent lots from exceeding the limit is necessary. The WIP levels of operations without time constraint are allocated by using the queueing theory.
    After setting the standard WIP level of all operations, a dispatching rule to maintain those standard WIP level should be applied. From literature review, there are many useful dispatching rules to reduce the mean cycle time and the standard deviation of the cycle time. But most of them still have some shortages. So in this study, a revised dispatching rule is developed to maintain those standard WIP levels of each workstation and operation, and the mean cycle time and the standard deviation of the cycle time can be effectively reduced.

    誌謝 I 摘要 II ABSTRACT III 目錄 IV 圖目錄 VII 表目錄 IX 第一章 緒論 1 1.1 研究背景 1 1.1.1半導體產業現況 1 1.1.2 半導體製造 1 1.1.3 生產週期時間的重要性 3 1.1.4 等候時間限制 9 1.1.5 批量加工機台與變異係數的關係 9 1.2 研究動機與目的 10 1.3 研究範圍、假設與限制 11 1.4 論文架構 12 第二章 文獻回顧 14 2.1 在製品存貨的重要性 14 2.2 訂定在製品存貨水準 17 2.3 投料與派工法則探討 18 2.3.1 投料法則 19 2.3.2 派工法則 19 2.4 等候時間限制 25 2.5 類神經網路 29 2.5.1 類神經網路介紹 29 2.5.2 類神經網路與迴歸分析之比較 30 2.6 X-FACTOR 31 2.7 小結 33 第三章 研究方法 35 3.1 將整廠的所有工作站作分類 36 3.2 訂定瓶頸工作站的最適在製品水準 37 3.2.1 BPNN模型運算與學習法則介紹 38 3.2.2 瓶頸站相關資料分析 41 3.2.3 變數選定與瓶頸站最適在製品水準訂定 43 3.3 訂定整廠最適的總在製品水準 45 3.4 訂定非瓶頸站在製品水準 46 3.4.1 訂定含等候時間限制作業之非瓶頸站在製品水準 47 3.4.2 訂定無等候時間限制作業之非瓶頸站在製品水準 49 3.5 派工法則 53 3.6 小結 55 第四章 實證研究 57 4.1 案例公司簡介 57 4.2 訂定瓶頸站之最適在製品水準 57 4.3 訂定整個廠的最適在製品水準 62 4.4 訂定含等候時間限制作業之非瓶頸站在製品數量上限 66 4.4.1 含等候時間限制作業之機台相關資訊 66 4.4.2 訂定存在等候時間限制作業的工作站在製品數量上限 68 4.5 訂定無等候時間限制作業之非瓶頸站在製品水準 72 4.6 模擬驗證 74 4.6.1 歷史在製品水準與新在製品水準的比較 74 4.6.2 兩層派工優序判斷 79 4.6.3 實務應用上的建議 91 第五章 結論與未來研究方向 93 參考文獻 95

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