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| 研究生： |
顏嘉鋒 Yen, Chia-Fung |
|---|---|
| 論文名稱： |
用於直接取樣單晶片雷達系統之連續漸進式類比數位轉換器設計 A SAR ADC Design for Director Sampling CMOS Radar System |
| 指導教授： |
朱大舜
Chu, Ta-Shun |
| 口試委員: |
吳仁銘
王毓駒 |
| 學位類別： |
碩士 Master |
| 系所名稱： |
電機資訊學院 - 電機工程學系 Department of Electrical Engineering |
| 論文出版年： | 2012 |
| 畢業學年度： | 100 |
| 語文別： | 英文 |
| 論文頁數： | 78 |
| 中文關鍵詞： | 連續漸進式類比數位轉換器 |
| 外文關鍵詞： | SAR ADC |
| 相關次數： | 點閱：3 下載：0 |
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研究所別：電機工程學系
論文名稱：用於直接取樣單晶片雷達系統之連續漸進式類比數位轉換器設計
指導教授：朱大舜 博士
研 究 生：9961546, 顏嘉鋒
隨著科技的進步，製程日漸更新，在同樣的面積下能夠設計的電路也越來越多，效能也越來越好。也隨著這樣的科技進步，許多人願意嘗試進行將大系統整合在一塊晶片的設計方式，而若是要將系統處理過的訊號放進電腦進行分析處理，則必須要使用類比數位轉換器。
本論文介紹三種不同的連續漸進式類比數位轉換器，每一個各有不同的用途，並比較其優缺點。
三種不同的連續漸進式類比數位轉換器分別為同步單端式，非同步單端式，非同步雙端式，進行介紹。其中個分別以聯電0.18微米製程，台積65奈米製程，台積65奈米製程下線驗證晶片，並分析其用於不同地方之功能以及效益。
三種連續漸進式類比數位轉換器分別經過量測以及模擬，第一種為8位元單端同步連續漸進式類比數位轉換器，經過量測後的結果其SNDR為48.43，有效位元數為7.75，DNL及INL分別為0.35~-0.57以及0.28~-0.57。第二種為10位元單端非同步連續漸進式類比數位轉換器，經過模擬結果SNDR為56.6，其有效位元數為9.12， DNL及INL分別為0.51~-0.5以及0.05~-0.5。第三種為10位元雙端非同步連續漸進式類比數位轉換器，經過模擬結果SNDR為61.30，其有效位元數為9.79，DNL及INL分別為0.002~-0.499以及0.52~-0.248。
三種連續漸進式類比數位轉換器分別有不同的效能，分別應用在不同的雷達系統之中，可因應不同的效能需求而讓使用者可以做選擇。
As technology advances, the process gradually updates, more and more circuits can be design in the same area,and the performance is getting better and better. With this scientific and technological progress, many people are willing to try to carry out large-scale system integrated in one chip design, but if they want to put the signal into a computer for analysis and processing, they must use the analog to digital converter.
This paper introduces three different continuous approximation analog-digital converters, each have different purposes, and their advantages and disadvantages.
Three different type continuous approximation analog to digital converter are synchronous single input, non-synchronous single input, non-synchronous differential input, are described. Which a UMC 0.18mm process, TSMC 65nm, the TSMC 65nm process tape out, and analyze its functionality and efficiency for different circuitry places.
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